[PATCH] D45259: [MC][Tablegen] Allow models to describe the retire control unit for llvm-mca.

[Andrea Di Biagio via Phabricator via llvm-commits]

andreadb created this revision.
andreadb added reviewers: RKSimon, courbet, spatel.
Herald added subscribers: gbedwell, tschuett.

This patch adds the ability to describe properties of the hardware retire control unit.

Tablegen class `RetireControlUnit` has been added for this purpose (see TargetSchedule.td).

A RetireControlUnit specifies the size of the reorder buffer, as well as the maximum number of opcodes that can be retired every cycle.

A zero (or negative) value for the reorder buffer size means: "the size is unknown". If the size is unknown, then llvm-mca defaults it to the value of field `SchedMachineModel::MicroOpBufferSize`.
A zero or negative number of opcodes retired per cycle means: "there is no restriction on the number of instructions that can be retired every cycle".

Models can optionally specify an instance of RetireControlUnit. There can only be up-to one RetireControlUnit definition per scheduling model.

Information related to the RCU (RetireControlUnit) is stored in (two new fields of) MCExtraProcessorInfo.
llvm-mca loads that information when it initializes the DispatchUnit / RetireControlUnit (see Dispatch.h/Dispatch.cpp).

This patch fixes PR36661.

Please let me know if okay to commit

-Andrea


https://reviews.llvm.org/D45259

Files:
  include/llvm/MC/MCSchedule.h
  include/llvm/Target/TargetSchedule.td
  lib/Target/X86/X86ScheduleBtVer2.td
  test/tools/llvm-mca/X86/BtVer2/dot-product.s
  test/tools/llvm-mca/X86/BtVer2/pipes-fpu.s
  test/tools/llvm-mca/X86/BtVer2/register-files-5.s
  tools/llvm-mca/Backend.h
  tools/llvm-mca/Dispatch.cpp
  tools/llvm-mca/Dispatch.h
  utils/TableGen/CodeGenSchedule.cpp
  utils/TableGen/CodeGenSchedule.h
  utils/TableGen/SubtargetEmitter.cpp

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