[llvm] r329200 - [llvm-exegesis] Temporarily disable a few tests.

[Clement Courbet via llvm-commits]

Author: courbet
Date: Wed Apr  4 07:32:09 2018
New Revision: 329200

URL: http://llvm.org/viewvc/llvm-project?rev=329200&view=rev
Log:
[llvm-exegesis] Temporarily disable a few tests.

These are failing on clang-ppc64le-linux-lnt, though the subdirectory is
not even supposed to be built in CMakeLists. Disable the tests until we
understand what's going on.

Modified:
    llvm/trunk/unittests/tools/llvm-exegesis/InMemoryAssemblerTest.cpp
    llvm/trunk/unittests/tools/llvm-exegesis/InstructionSnippetGeneratorTest.cpp

Modified: llvm/trunk/unittests/tools/llvm-exegesis/InMemoryAssemblerTest.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/unittests/tools/llvm-exegesis/InMemoryAssemblerTest.cpp?rev=329200&r1=329199&r2=329200&view=diff
==============================================================================
--- llvm/trunk/unittests/tools/llvm-exegesis/InMemoryAssemblerTest.cpp (original)
+++ llvm/trunk/unittests/tools/llvm-exegesis/InMemoryAssemblerTest.cpp Wed Apr  4 07:32:09 2018
@@ -59,7 +59,7 @@ private:
   const std::string CpuName;
 };
 
-TEST_F(MachineFunctionGeneratorTest, JitFunction) {
+TEST_F(MachineFunctionGeneratorTest, DISABLED_JitFunction) {
   JitFunctionContext Context(createTargetMachine());
   JitFunction Function(std::move(Context), {});
   ASSERT_THAT(Function.getFunctionBytes().str(), ElementsAre(0xc3));
@@ -68,7 +68,7 @@ TEST_F(MachineFunctionGeneratorTest, Jit
   // Function();
 }
 
-TEST_F(MachineFunctionGeneratorTest, JitFunctionXOR32rr) {
+TEST_F(MachineFunctionGeneratorTest, DISABLED_JitFunctionXOR32rr) {
   JitFunctionContext Context(createTargetMachine());
   JitFunction Function(
       std::move(Context),
@@ -77,7 +77,7 @@ TEST_F(MachineFunctionGeneratorTest, Jit
   // Function();
 }
 
-TEST_F(MachineFunctionGeneratorTest, JitFunctionMOV64ri) {
+TEST_F(MachineFunctionGeneratorTest, DISABLED_JitFunctionMOV64ri) {
   JitFunctionContext Context(createTargetMachine());
   JitFunction Function(std::move(Context),
                        {MCInstBuilder(MOV64ri32).addReg(RAX).addImm(42)});
@@ -86,7 +86,7 @@ TEST_F(MachineFunctionGeneratorTest, Jit
   // Function();
 }
 
-TEST_F(MachineFunctionGeneratorTest, JitFunctionMOV32ri) {
+TEST_F(MachineFunctionGeneratorTest, DISABLED_JitFunctionMOV32ri) {
   JitFunctionContext Context(createTargetMachine());
   JitFunction Function(std::move(Context),
                        {MCInstBuilder(MOV32ri).addReg(EAX).addImm(42)});

Modified: llvm/trunk/unittests/tools/llvm-exegesis/InstructionSnippetGeneratorTest.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/unittests/tools/llvm-exegesis/InstructionSnippetGeneratorTest.cpp?rev=329200&r1=329199&r2=329200&view=diff
==============================================================================
--- llvm/trunk/unittests/tools/llvm-exegesis/InstructionSnippetGeneratorTest.cpp (original)
+++ llvm/trunk/unittests/tools/llvm-exegesis/InstructionSnippetGeneratorTest.cpp Wed Apr  4 07:32:09 2018
@@ -85,7 +85,7 @@ MATCHER_P2(EqVarAssignement, VariableInd
 
 size_t returnIndexZero(const size_t UpperBound) { return 0; }
 
-TEST_F(MCInstrDescViewTest, XOR64rr) {
+TEST_F(MCInstrDescViewTest, DISABLED_XOR64rr) {
   const llvm::MCInstrDesc &InstrDesc = InstrInfo->get(llvm::X86::XOR64rr);
   const auto Vars =
       getVariables(*RegInfo, InstrDesc, llvm::BitVector(RegInfo->getNumRegs()));
@@ -145,7 +145,7 @@ TEST_F(MCInstrDescViewTest, XOR64rr) {
   EXPECT_THAT(Inst.getOperand(2), llvm::MCOperand::createReg(RAX));
 }
 
-TEST_F(MCInstrDescViewTest, AAA) {
+TEST_F(MCInstrDescViewTest, DISABLED_AAA) {
   const llvm::MCInstrDesc &InstrDesc = InstrInfo->get(llvm::X86::AAA);
   const auto Vars =
       getVariables(*RegInfo, InstrDesc, llvm::BitVector(RegInfo->getNumRegs()));
@@ -191,7 +191,7 @@ TEST_F(MCInstrDescViewTest, AAA) {
   EXPECT_THAT(Inst.getNumOperands(), 0) << "All operands are implicit";
 }
 
-TEST_F(MCInstrDescViewTest, ReservedRegisters) {
+TEST_F(MCInstrDescViewTest, DISABLED_ReservedRegisters) {
   llvm::BitVector ReservedRegisters(RegInfo->getNumRegs());
 
   const llvm::MCInstrDesc &InstrDesc = InstrInfo->get(llvm::X86::XOR64rr);