[PATCH] D45229: [MI-sched] schedule following instruction latencies

[Matthias Braun via Phabricator via llvm-commits]

MatzeB added a comment.

or

  $ clang -arch arm64 -O3 -S -o- t.c -mcpu=generic
  ...
  	ldrb		w8, [x1]
  	ldrb	w9, [x1, #1]
  	ldrb	w10, [x1, #2]
  	ldrb	w11, [x1, #3]
  	strb		w8, [x0]
  	strb	w9, [x0, #1]
  	strb	w10, [x0, #2]
  	strb	w11, [x0, #3]
  	ret



- Are you sure you are using a good scheduling model?
- A change like this needs a lot of benchmarking. In my experience real world looses all too fast when additional latency heuristics fight against register pressure. (See also the code around tryLatency()).


https://reviews.llvm.org/D45229