[PATCH] D44980: [MC][Tblgen] Allow the definition of processor register files in the scheduling model for llvm-mca

[Andrea Di Biagio via Phabricator via llvm-commits]

andreadb updated this revision to Diff 140760.
andreadb added a comment.

Patch updated.

Addressed review comments from Clement.

Added an invalid register file entry in the tablegen'd table of register file descriptors.

This is what we get on BtVer2 with this patch (in X86GenSubtargetInfo.inc):

  // {RegisterClassID, Register Cost}
  static const llvm::MCRegisterCostEntry BtVer2ModelRegisterCosts[] = {
    { X86::VR64RegClassID, 1},
    { X86::VR128RegClassID, 1},
    { X86::VR256RegClassID, 2},
    { X86::GR8RegClassID, 1},
    { X86::GR16RegClassID, 1},
    { X86::GR32RegClassID, 1},
    { X86::GR64RegClassID, 1},
    { X86::CCRRegClassID, 1},
  };
  
   // {Name, #PhysRegs, #CostEntries, IndexToCostTbl}
  static const llvm::MCRegisterFileDesc BtVer2ModelRegisterFiles[] = {
    { "InvalidRegisterFile", 0, 0, 0 },
    { "FpuPRF", 72, 3, 0},
    { "IntegerPRF", 64, 5, 3},
  };
  
  static const llvm::MCExtraProcessorInfo BtVer2ModelExtraInfo = {
    BtVer2ModelRegisterFiles,
    3, // Number of register files.
    BtVer2ModelRegisterCosts,
    8 // Number of register cost entries.
  };

A register file with zero physical registers is treated by llvm-mca as an invalid register file. So, entry #0 from the `BtVer2ModelRegisterFiles` table is never used.


https://reviews.llvm.org/D44980

Files:
  include/llvm/MC/MCSchedule.h
  include/llvm/Target/TargetSchedule.td
  lib/Target/X86/X86ScheduleBtVer2.td
  test/tools/llvm-mca/X86/BtVer2/register-files-1.s
  test/tools/llvm-mca/X86/BtVer2/register-files-2.s
  test/tools/llvm-mca/X86/BtVer2/register-files-3.s
  test/tools/llvm-mca/X86/BtVer2/register-files-4.s
  test/tools/llvm-mca/X86/BtVer2/register-files-5.s
  tools/llvm-mca/Backend.h
  tools/llvm-mca/BackendStatistics.cpp
  tools/llvm-mca/BackendStatistics.h
  tools/llvm-mca/Dispatch.cpp
  tools/llvm-mca/Dispatch.h
  utils/TableGen/CodeGenSchedule.cpp
  utils/TableGen/CodeGenSchedule.h
  utils/TableGen/SubtargetEmitter.cpp

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