[llvm] r328962 - [X86][Silvermont] Use correct latency and throughput information for divide and square root in the scheduler model.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Sun Apr 1 23:34:17 PDT 2018
Author: ctopper
Date: Sun Apr 1 23:34:16 2018
New Revision: 328962
URL: http://llvm.org/viewvc/llvm-project?rev=328962&view=rev
Log:
[X86][Silvermont] Use correct latency and throughput information for divide and square root in the scheduler model.
Data taken from Table 16-17 in the Intel Optimization Manual.
Modified:
llvm/trunk/lib/Target/X86/X86ScheduleSLM.td
llvm/trunk/test/CodeGen/X86/sse-schedule.ll
llvm/trunk/test/CodeGen/X86/sse2-schedule.ll
Modified: llvm/trunk/lib/Target/X86/X86ScheduleSLM.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ScheduleSLM.td?rev=328962&r1=328961&r2=328962&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ScheduleSLM.td (original)
+++ llvm/trunk/lib/Target/X86/X86ScheduleSLM.td Sun Apr 1 23:34:16 2018
@@ -249,4 +249,119 @@ defm : SLMWriteResPair<WriteFShuffle256,
defm : SLMWriteResPair<WriteShuffle256, [SLM_FPC_RSV0], 1>;
defm : SLMWriteResPair<WriteVarVecShift, [SLM_FPC_RSV0], 1>;
defm : SLMWriteResPair<WriteFMA, [SLM_FPC_RSV0], 1>;
+
+// Instruction overrides
+
+def SLMriteResGroup1 : SchedWriteRes<[SLM_FPC_RSV0,SLMFPDivider]> {
+ let Latency = 69;
+ let NumMicroOps = 1;
+ let ResourceCycles = [1,69];
+}
+def: InstRW<[SLMriteResGroup1], (instregex "(V?)DIVPDrr")>;
+
+def SLMriteResGroup2 : SchedWriteRes<[SLM_FPC_RSV0,SLMFPDivider]> {
+ let Latency = 39;
+ let NumMicroOps = 1;
+ let ResourceCycles = [1,39];
+}
+def: InstRW<[SLMriteResGroup2], (instregex "(V?)DIVPSrr")>;
+
+def SLMriteResGroup3 : SchedWriteRes<[SLM_FPC_RSV0,SLMFPDivider]> {
+ let Latency = 34;
+ let NumMicroOps = 1;
+ let ResourceCycles = [1,32];
+}
+def: InstRW<[SLMriteResGroup3], (instregex "(V?)DIVSDrr")>;
+
+def SLMriteResGroup4 : SchedWriteRes<[SLM_FPC_RSV0,SLMFPDivider]> {
+ let Latency = 19;
+ let NumMicroOps = 1;
+ let ResourceCycles = [1,17];
+}
+def: InstRW<[SLMriteResGroup4], (instregex "(V?)DIVSSrr")>;
+
+def SLMriteResGroup5 : SchedWriteRes<[SLM_MEC_RSV,SLM_FPC_RSV0,SLMFPDivider]> {
+ let Latency = 72;
+ let NumMicroOps = 1;
+ let ResourceCycles = [1,1,69];
+}
+def: InstRW<[SLMriteResGroup5], (instregex "(V?)DIVPDrm")>;
+
+def SLMriteResGroup6 : SchedWriteRes<[SLM_MEC_RSV,SLM_FPC_RSV0,SLMFPDivider]> {
+ let Latency = 42;
+ let NumMicroOps = 1;
+ let ResourceCycles = [1,1,39];
+}
+def: InstRW<[SLMriteResGroup6], (instregex "(V?)DIVPSrm")>;
+
+def SLMriteResGroup7 : SchedWriteRes<[SLM_MEC_RSV,SLM_FPC_RSV0,SLMFPDivider]> {
+ let Latency = 37;
+ let NumMicroOps = 1;
+ let ResourceCycles = [1,1,32];
+}
+def: InstRW<[SLMriteResGroup7], (instregex "(V?)DIVSDrm")>;
+
+def SLMriteResGroup8 : SchedWriteRes<[SLM_MEC_RSV,SLM_FPC_RSV0,SLMFPDivider]> {
+ let Latency = 22;
+ let NumMicroOps = 1;
+ let ResourceCycles = [1,1,17];
+}
+def: InstRW<[SLMriteResGroup8], (instregex "(V?)DIVSSrm")>;
+
+def SLMriteResGroup9 : SchedWriteRes<[SLM_FPC_RSV0,SLMFPDivider]> {
+ let Latency = 71;
+ let NumMicroOps = 1;
+ let ResourceCycles = [1,70];
+}
+def: InstRW<[SLMriteResGroup9], (instregex "(V?)SQRTPDr")>;
+
+def SLMriteResGroup10 : SchedWriteRes<[SLM_FPC_RSV0,SLMFPDivider]> {
+ let Latency = 41;
+ let NumMicroOps = 1;
+ let ResourceCycles = [1,40];
+}
+def: InstRW<[SLMriteResGroup10], (instregex "(V?)SQRTPSr")>;
+
+def SLMriteResGroup11 : SchedWriteRes<[SLM_FPC_RSV0,SLMFPDivider]> {
+ let Latency = 35;
+ let NumMicroOps = 1;
+ let ResourceCycles = [1,35];
+}
+def: InstRW<[SLMriteResGroup11], (instregex "(V?)SQRTSDr")>;
+
+def SLMriteResGroup12 : SchedWriteRes<[SLM_FPC_RSV0,SLMFPDivider]> {
+ let Latency = 20;
+ let NumMicroOps = 1;
+ let ResourceCycles = [1,20];
+}
+def: InstRW<[SLMriteResGroup12], (instregex "(V?)SQRTSSr")>;
+
+def SLMriteResGroup13 : SchedWriteRes<[SLM_MEC_RSV,SLM_FPC_RSV0,SLMFPDivider]> {
+ let Latency = 74;
+ let NumMicroOps = 1;
+ let ResourceCycles = [1,70];
+}
+def: InstRW<[SLMriteResGroup13], (instregex "(V?)SQRTPDm")>;
+
+def SLMriteResGroup14 : SchedWriteRes<[SLM_MEC_RSV,SLM_FPC_RSV0,SLMFPDivider]> {
+ let Latency = 44;
+ let NumMicroOps = 1;
+ let ResourceCycles = [1,1,40];
+}
+def: InstRW<[SLMriteResGroup14], (instregex "(V?)SQRTPSm")>;
+
+def SLMriteResGroup15 : SchedWriteRes<[SLM_MEC_RSV,SLM_FPC_RSV0,SLMFPDivider]> {
+ let Latency = 38;
+ let NumMicroOps = 1;
+ let ResourceCycles = [1,1,35];
+}
+def: InstRW<[SLMriteResGroup15], (instregex "(V?)SQRTSDm")>;
+
+def SLMriteResGroup16 : SchedWriteRes<[SLM_MEC_RSV,SLM_FPC_RSV0,SLMFPDivider]> {
+ let Latency = 23;
+ let NumMicroOps = 1;
+ let ResourceCycles = [1,1,20];
+}
+def: InstRW<[SLMriteResGroup16], (instregex "(V?)SQRTSSm")>;
+
} // SchedModel
Modified: llvm/trunk/test/CodeGen/X86/sse-schedule.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse-schedule.ll?rev=328962&r1=328961&r2=328962&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/sse-schedule.ll (original)
+++ llvm/trunk/test/CodeGen/X86/sse-schedule.ll Sun Apr 1 23:34:16 2018
@@ -1735,8 +1735,8 @@ define <4 x float> @test_divps(<4 x floa
;
; SLM-LABEL: test_divps:
; SLM: # %bb.0:
-; SLM-NEXT: divps %xmm1, %xmm0 # sched: [34:34.00]
-; SLM-NEXT: divps (%rdi), %xmm0 # sched: [37:34.00]
+; SLM-NEXT: divps %xmm1, %xmm0 # sched: [39:39.00]
+; SLM-NEXT: divps (%rdi), %xmm0 # sched: [42:39.00]
; SLM-NEXT: retq # sched: [4:1.00]
;
; SANDY-SSE-LABEL: test_divps:
@@ -1843,8 +1843,8 @@ define float @test_divss(float %a0, floa
;
; SLM-LABEL: test_divss:
; SLM: # %bb.0:
-; SLM-NEXT: divss %xmm1, %xmm0 # sched: [34:34.00]
-; SLM-NEXT: divss (%rdi), %xmm0 # sched: [37:34.00]
+; SLM-NEXT: divss %xmm1, %xmm0 # sched: [19:17.00]
+; SLM-NEXT: divss (%rdi), %xmm0 # sched: [22:17.00]
; SLM-NEXT: retq # sched: [4:1.00]
;
; SANDY-SSE-LABEL: test_divss:
@@ -4914,8 +4914,8 @@ define <4 x float> @test_sqrtps(<4 x flo
;
; SLM-LABEL: test_sqrtps:
; SLM: # %bb.0:
-; SLM-NEXT: sqrtps (%rdi), %xmm1 # sched: [18:1.00]
-; SLM-NEXT: sqrtps %xmm0, %xmm0 # sched: [15:1.00]
+; SLM-NEXT: sqrtps (%rdi), %xmm1 # sched: [44:40.00]
+; SLM-NEXT: sqrtps %xmm0, %xmm0 # sched: [41:40.00]
; SLM-NEXT: addps %xmm0, %xmm1 # sched: [3:1.00]
; SLM-NEXT: movaps %xmm1, %xmm0 # sched: [1:0.50]
; SLM-NEXT: retq # sched: [4:1.00]
@@ -5047,8 +5047,8 @@ define <4 x float> @test_sqrtss(<4 x flo
; SLM-LABEL: test_sqrtss:
; SLM: # %bb.0:
; SLM-NEXT: movaps (%rdi), %xmm1 # sched: [3:1.00]
-; SLM-NEXT: sqrtss %xmm0, %xmm0 # sched: [15:1.00]
-; SLM-NEXT: sqrtss %xmm1, %xmm1 # sched: [15:1.00]
+; SLM-NEXT: sqrtss %xmm0, %xmm0 # sched: [20:20.00]
+; SLM-NEXT: sqrtss %xmm1, %xmm1 # sched: [20:20.00]
; SLM-NEXT: addps %xmm1, %xmm0 # sched: [3:1.00]
; SLM-NEXT: retq # sched: [4:1.00]
;
Modified: llvm/trunk/test/CodeGen/X86/sse2-schedule.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse2-schedule.ll?rev=328962&r1=328961&r2=328962&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/sse2-schedule.ll (original)
+++ llvm/trunk/test/CodeGen/X86/sse2-schedule.ll Sun Apr 1 23:34:16 2018
@@ -3176,8 +3176,8 @@ define <2 x double> @test_divpd(<2 x dou
;
; SLM-LABEL: test_divpd:
; SLM: # %bb.0:
-; SLM-NEXT: divpd %xmm1, %xmm0 # sched: [34:34.00]
-; SLM-NEXT: divpd (%rdi), %xmm0 # sched: [37:34.00]
+; SLM-NEXT: divpd %xmm1, %xmm0 # sched: [69:69.00]
+; SLM-NEXT: divpd (%rdi), %xmm0 # sched: [72:69.00]
; SLM-NEXT: retq # sched: [4:1.00]
;
; SANDY-SSE-LABEL: test_divpd:
@@ -3284,8 +3284,8 @@ define double @test_divsd(double %a0, do
;
; SLM-LABEL: test_divsd:
; SLM: # %bb.0:
-; SLM-NEXT: divsd %xmm1, %xmm0 # sched: [34:34.00]
-; SLM-NEXT: divsd (%rdi), %xmm0 # sched: [37:34.00]
+; SLM-NEXT: divsd %xmm1, %xmm0 # sched: [34:32.00]
+; SLM-NEXT: divsd (%rdi), %xmm0 # sched: [37:32.00]
; SLM-NEXT: retq # sched: [4:1.00]
;
; SANDY-SSE-LABEL: test_divsd:
@@ -14156,8 +14156,8 @@ define <2 x double> @test_sqrtpd(<2 x do
;
; SLM-LABEL: test_sqrtpd:
; SLM: # %bb.0:
-; SLM-NEXT: sqrtpd (%rdi), %xmm1 # sched: [18:1.00]
-; SLM-NEXT: sqrtpd %xmm0, %xmm0 # sched: [15:1.00]
+; SLM-NEXT: sqrtpd (%rdi), %xmm1 # sched: [74:70.00]
+; SLM-NEXT: sqrtpd %xmm0, %xmm0 # sched: [71:70.00]
; SLM-NEXT: addpd %xmm0, %xmm1 # sched: [3:1.00]
; SLM-NEXT: movapd %xmm1, %xmm0 # sched: [1:0.50]
; SLM-NEXT: retq # sched: [4:1.00]
@@ -14289,8 +14289,8 @@ define <2 x double> @test_sqrtsd(<2 x do
; SLM-LABEL: test_sqrtsd:
; SLM: # %bb.0:
; SLM-NEXT: movapd (%rdi), %xmm1 # sched: [3:1.00]
-; SLM-NEXT: sqrtsd %xmm0, %xmm0 # sched: [15:1.00]
-; SLM-NEXT: sqrtsd %xmm1, %xmm1 # sched: [15:1.00]
+; SLM-NEXT: sqrtsd %xmm0, %xmm0 # sched: [35:35.00]
+; SLM-NEXT: sqrtsd %xmm1, %xmm1 # sched: [35:35.00]
; SLM-NEXT: addpd %xmm1, %xmm0 # sched: [3:1.00]
; SLM-NEXT: retq # sched: [4:1.00]
;
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