[llvm] r328961 - [X86][SkylakeServer] Correct throughput for 512-bit sqrt and divide.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Sun Apr 1 22:54:34 PDT 2018
Author: ctopper
Date: Sun Apr 1 22:54:34 2018
New Revision: 328961
URL: http://llvm.org/viewvc/llvm-project?rev=328961&view=rev
Log:
[X86][SkylakeServer] Correct throughput for 512-bit sqrt and divide.
Data taken from the AVX512_SKX_PortAssign spreadsheet at http://instlatx64.atw.hu/
Modified:
llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td
llvm/trunk/test/CodeGen/X86/avx512-schedule.ll
Modified: llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td?rev=328961&r1=328960&r2=328961&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td Sun Apr 1 22:54:34 2018
@@ -5685,13 +5685,12 @@ def SKXWriteResGroup209_1 : SchedWriteRe
}
def: InstRW<[SKXWriteResGroup209_1], (instregex "VSQRTPS(Y|Z256)m")>;
-//FIXME
-def SKXWriteResGroup210 : SchedWriteRes<[SKXPort0,SKXPort015]> {
- let Latency = 19;
+def SKXWriteResGroup210 : SchedWriteRes<[SKXPort0,SKXPort5,SKXFPDivider]> {
+ let Latency = 20;
let NumMicroOps = 3;
- let ResourceCycles = [2,1];
+ let ResourceCycles = [2,1,12];
}
-def: InstRW<[SKXWriteResGroup210], (instregex "VSQRTPSZr(b?)")>;
+def: InstRW<[SKXWriteResGroup210], (instregex "VSQRTPSZr")>;
def SKXWriteResGroup211 : SchedWriteRes<[SKXPort23,SKXPort015]> {
let Latency = 19;
@@ -5847,14 +5846,19 @@ def SKXWriteResGroup226 : SchedWriteRes<
}
def: InstRW<[SKXWriteResGroup226], (instregex "(V?)SQRTSD(Z?)m")>;
-// FIXME
-def SKXWriteResGroup227 : SchedWriteRes<[SKXPort0,SKXPort015]> {
+def SKXWriteResGroup227 : SchedWriteRes<[SKXPort0,SKXPort5,SKXFPDivider]> {
let Latency = 23;
let NumMicroOps = 3;
- let ResourceCycles = [2,1];
+ let ResourceCycles = [2,1,16];
+}
+def: InstRW<[SKXWriteResGroup227], (instregex "VDIVPDZrr")>;
+
+def SKXWriteResGroup227_1 : SchedWriteRes<[SKXPort0,SKXPort5,SKXFPDivider]> {
+ let Latency = 18;
+ let NumMicroOps = 3;
+ let ResourceCycles = [2,1,10];
}
-def: InstRW<[SKXWriteResGroup227], (instregex "VDIVPDZrr",
- "VDIVPSZrr")>;
+def: InstRW<[SKXWriteResGroup227_1], (instregex "VDIVPSZrr")>;
def SKXWriteResGroup228 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort5,SKXPort23,SKXPort237,SKXPort06,SKXPort0156]> {
let Latency = 23;
@@ -5870,11 +5874,10 @@ def SKXWriteResGroup229 : SchedWriteRes<
}
def: InstRW<[SKXWriteResGroup229], (instregex "(V?)SQRTPD(Z128)?m")>;
-//FIXME
-def SKXWriteResGroup230 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort015]> {
- let Latency = 24;
+def SKXWriteResGroup230 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort5,SKXFPDivider]> {
+ let Latency = 25;
let NumMicroOps = 4;
- let ResourceCycles = [2,1,1];
+ let ResourceCycles = [2,1,1,10];
}
def: InstRW<[SKXWriteResGroup230], (instregex "VDIVPSZrm(b?)")>;
@@ -5904,11 +5907,10 @@ def: InstRW<[SKXWriteResGroup234], (inst
VPGATHERQDZrm,
VPGATHERQQZ256rm)>;
-// FIXME
-def SKXWriteResGroup237 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort015]> {
- let Latency = 26;
+def SKXWriteResGroup237 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort5,SKXFPDivider]> {
+ let Latency = 27;
let NumMicroOps = 4;
- let ResourceCycles = [2,1,1];
+ let ResourceCycles = [2,1,1,12];
}
def: InstRW<[SKXWriteResGroup237], (instregex "VSQRTPSZm(b?)")>;
@@ -5960,11 +5962,10 @@ def SKXWriteResGroup243 : SchedWriteRes<
def: InstRW<[SKXWriteResGroup243], (instregex "DIVR_FI16m",
"DIVR_FI32m")>;
-// FIXME
-def SKXWriteResGroup244 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort015]> {
+def SKXWriteResGroup244 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort5,SKXFPDivider]> {
let Latency = 30;
let NumMicroOps = 4;
- let ResourceCycles = [2,1,1];
+ let ResourceCycles = [2,1,1,16];
}
def: InstRW<[SKXWriteResGroup244], (instregex "VDIVPDZrm(b?)")>;
@@ -5976,11 +5977,10 @@ def SKXWriteResGroup245 : SchedWriteRes<
def: InstRW<[SKXWriteResGroup245], (instrs VGATHERDPSZrm,
VPGATHERDDZrm)>;
-// FIXME
-def SKXWriteResGroup246 : SchedWriteRes<[SKXPort0,SKXPort015]> {
- let Latency = 31;
+def SKXWriteResGroup246 : SchedWriteRes<[SKXPort0,SKXPort5,SKXFPDivider]> {
+ let Latency = 32;
let NumMicroOps = 3;
- let ResourceCycles = [2,1];
+ let ResourceCycles = [2,1,24];
}
def: InstRW<[SKXWriteResGroup246], (instregex "VSQRTPDZr")>;
@@ -6015,11 +6015,10 @@ def SKXWriteResGroup250 : SchedWriteRes<
}
def: InstRW<[SKXWriteResGroup250], (instregex "XRSTOR(64)?")>;
-// FIXME
-def SKXWriteResGroup251 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort015]> {
- let Latency = 38;
+def SKXWriteResGroup251 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort5,SKXFPDivider]> {
+ let Latency = 39;
let NumMicroOps = 4;
- let ResourceCycles = [2,1,1];
+ let ResourceCycles = [2,1,1,24];
}
def: InstRW<[SKXWriteResGroup251], (instregex "VSQRTPDZm(b?)")>;
Modified: llvm/trunk/test/CodeGen/X86/avx512-schedule.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512-schedule.ll?rev=328961&r1=328960&r2=328961&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx512-schedule.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx512-schedule.ll Sun Apr 1 22:54:34 2018
@@ -236,7 +236,7 @@ define <8 x double> @divpd512(<8 x doubl
;
; SKX-LABEL: divpd512:
; SKX: # %bb.0: # %entry
-; SKX-NEXT: vdivpd %zmm0, %zmm1, %zmm0 # sched: [23:2.00]
+; SKX-NEXT: vdivpd %zmm0, %zmm1, %zmm0 # sched: [23:16.00]
; SKX-NEXT: retq # sched: [7:1.00]
entry:
%div.i = fdiv <8 x double> %x, %y
@@ -251,7 +251,7 @@ define <8 x double> @divpd512fold(<8 x d
;
; SKX-LABEL: divpd512fold:
; SKX: # %bb.0: # %entry
-; SKX-NEXT: vdivpd {{.*}}(%rip), %zmm0, %zmm0 # sched: [30:2.00]
+; SKX-NEXT: vdivpd {{.*}}(%rip), %zmm0, %zmm0 # sched: [30:16.00]
; SKX-NEXT: retq # sched: [7:1.00]
entry:
%div.i = fdiv <8 x double> %y, <double 4.500000e+00, double 3.400000e+00, double 2.300000e+00, double 1.200000e+00, double 4.500000e+00, double 3.400000e+00, double 2.300000e+00, double 1.200000e+00>
@@ -266,7 +266,7 @@ define <16 x float> @divps512(<16 x floa
;
; SKX-LABEL: divps512:
; SKX: # %bb.0: # %entry
-; SKX-NEXT: vdivps %zmm0, %zmm1, %zmm0 # sched: [23:2.00]
+; SKX-NEXT: vdivps %zmm0, %zmm1, %zmm0 # sched: [18:10.00]
; SKX-NEXT: retq # sched: [7:1.00]
entry:
%div.i = fdiv <16 x float> %x, %y
@@ -281,7 +281,7 @@ define <16 x float> @divps512fold(<16 x
;
; SKX-LABEL: divps512fold:
; SKX: # %bb.0: # %entry
-; SKX-NEXT: vdivps {{.*}}(%rip), %zmm0, %zmm0 # sched: [24:2.00]
+; SKX-NEXT: vdivps {{.*}}(%rip), %zmm0, %zmm0 # sched: [25:10.00]
; SKX-NEXT: retq # sched: [7:1.00]
entry:
%div.i = fdiv <16 x float> %y, <float 4.500000e+00, float 0x400B333340000000, float 0x4002666660000000, float 0x3FF3333340000000, float 4.500000e+00, float 4.500000e+00, float 0x4002666660000000, float 0x3FF3333340000000, float 4.500000e+00, float 0x400B333340000000, float 0x4002666660000000, float 0x3FF3333340000000, float 4.500000e+00, float 4.500000e+00, float 0x4002666660000000, float 0x3FF3333340000000>
@@ -605,7 +605,7 @@ define <16 x float> @sqrtD(<16 x float>
;
; SKX-LABEL: sqrtD:
; SKX: # %bb.0:
-; SKX-NEXT: vsqrtps %zmm0, %zmm0 # sched: [19:2.00]
+; SKX-NEXT: vsqrtps %zmm0, %zmm0 # sched: [20:12.00]
; SKX-NEXT: retq # sched: [7:1.00]
%b = call <16 x float> @llvm.sqrt.v16f32(<16 x float> %a)
ret <16 x float> %b
@@ -620,7 +620,7 @@ define <8 x double> @sqrtE(<8 x double>
;
; SKX-LABEL: sqrtE:
; SKX: # %bb.0:
-; SKX-NEXT: vsqrtpd %zmm0, %zmm0 # sched: [31:2.00]
+; SKX-NEXT: vsqrtpd %zmm0, %zmm0 # sched: [32:24.00]
; SKX-NEXT: retq # sched: [7:1.00]
%b = call <8 x double> @llvm.sqrt.v8f64(<8 x double> %a)
ret <8 x double> %b
@@ -844,7 +844,7 @@ define <16 x float> @test_mask_vdivps(<1
; SKX-LABEL: test_mask_vdivps:
; SKX: # %bb.0:
; SKX-NEXT: vptestmd %zmm3, %zmm3, %k1 # sched: [3:1.00]
-; SKX-NEXT: vdivps %zmm2, %zmm1, %zmm0 {%k1} # sched: [23:2.00]
+; SKX-NEXT: vdivps %zmm2, %zmm1, %zmm0 {%k1} # sched: [18:10.00]
; SKX-NEXT: retq # sched: [7:1.00]
%mask = icmp ne <16 x i32> %mask1, zeroinitializer
%x = fdiv <16 x float> %i, %j
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