[PATCH] D44972: [X86] Add SchedRW for PMULLD

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: lib/Target/X86/X86SchedSkylakeServer.td:163
 defm : SKXWriteResPair<WriteVecIMul,  [SKXPort0],   5>; // Vector integer multiply.
+defm : SKXWriteResPair<WritePMULLD,   [SKXPort015], 10, [2], 2>; // Vector integer multiply.
 defm : SKXWriteResPair<WriteShuffle,  [SKXPort5],  1>; // Vector shuffles.
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courbet wrote:
> I don't have a skylake server to test that, but I'm surprised that this is different from SKL. Is this a typo ?
SKX adds an extra FMA unit and vector multiplier in port 5 for AVX512. 512-bit operations combine the 256-bit port0 and 1 units. So an extra unit was added to maintain 2 ports for 512-bit.

I’m not sure the port 5 unit can be used for 128 and 256 bit, but the scheduler model thinks so. The scheduler model definitely doesn’t model 512 bit correctly, but that’s a larger problem than I want to fix here.


https://reviews.llvm.org/D44972