[PATCH] D44401: [AMDGPU] Always use IDX for load/store format intrinsics.

[Tim Renouf via Phabricator via llvm-commits]

tpr added a comment.

Also (in terms of extra changes needed in buffer intrinsics over and above this change):

David Stuttard pointed me at
https://reviews.llvm.org/D30687
in which Tom Stellard pointed out that the way the buffer intrinsics conflate the three offsets (inst_offset, sgpr_offset and vgpr_offset) breaks swizzling, and possibly range checking in swizzling too.

So the suggestion is to have new intrinsics with the three offsets in separate args, in the same way as David's tbuffer intrinsic. Then the new intrinsics would also need to have raw and structured variants.


Repository:
  rL LLVM

https://reviews.llvm.org/D44401