[PATCH] D44401: [AMDGPU] Always use IDX for load/store format intrinsics.

Tim Renouf via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Tue Mar 27 01:06:52 PDT 2018


tpr added a comment.

I don't have any objection to this change going in, but I think we need more:

1. LLPC generates indexed atomic ops. This change does not fix that. We have a case where LLVM optimizes an index that is constant 0 to idxen=0, causing a breakage. But probably not all atomic ops are intended to be indexed.

2. This change doesn't do anything to tbuffer ops.

3. Longer term, surely it makes sense to represent the full semantic capability of the ISA by having non-indexed and indexed (raw and structured) variants of all of the intrinsics. That could be done compatibly after this change by assuming the formatted buffer ops are structured and introducing raw variants, and assuming the other buffer ops are raw and introducing structured variants.


Repository:
  rL LLVM

https://reviews.llvm.org/D44401





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