[PATCH] D44879: [X86] Add WriteBitScan/WriteLZCNT/WriteTZCNT/WritePOPCNT scheduler classes (PR36881)

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: lib/Target/X86/X86SchedSandyBridge.td:117
+defm : SBWriteResPair<WriteBitScan, [SBPort1], 3, [1], 1, 5>;
+defm : SBWriteResPair<WriteLZCNT,   [SBPort1], 3>;
+defm : SBWriteResPair<WriteTZCNT,   [SBPort1], 3>;
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Why are these not load latency 5? Aside from SNB not having these instructions?


Repository:
  rL LLVM

https://reviews.llvm.org/D44879