[llvm] r328452 - [X86][SkylakeServer] Merge multiple instregex. NFCI

[Simon Pilgrim via llvm-commits]

Author: rksimon
Date: Sun Mar 25 10:25:37 2018
New Revision: 328452

URL: http://llvm.org/viewvc/llvm-project?rev=328452&view=rev
Log:
[X86][SkylakeServer] Merge multiple instregex. NFCI

Modified:
    llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td

Modified: llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td?rev=328452&r1=328451&r2=328452&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td Sun Mar 25 10:25:37 2018
@@ -19,7 +19,7 @@ def SkylakeServerModel : SchedMachineMod
   let MicroOpBufferSize = 224; // Based on the reorder buffer.
   let LoadLatency = 5;
   let MispredictPenalty = 14;
-  
+
   // Based on the LSD (loop-stream detector) queue size and benchmarking data.
   let LoopMicroOpBufferSize = 50;
 
@@ -104,7 +104,7 @@ def : WriteRes<WriteRMW, [SKXPort4]>;
 defm : SKXWriteResPair<WriteALU,   [SKXPort0156], 1>; // Simple integer ALU op.
 defm : SKXWriteResPair<WriteIMul,  [SKXPort1],   3>; // Integer multiplication.
 def : WriteRes<WriteIMulH, []> { let Latency = 3; } // Integer multiplication, high part.
-def SKXDivider : ProcResource<1>; // Integer division issued on port 0.     
+def SKXDivider : ProcResource<1>; // Integer division issued on port 0.
 def : WriteRes<WriteIDiv, [SKXPort0, SKXDivider]> { // Integer division.
   let Latency = 25;
   let ResourceCycles = [1, 10];
@@ -185,7 +185,7 @@ def : WriteRes<WritePCmpIStrMLd, [SKXPor
   let Latency = 16;
   let NumMicroOps = 4;
   let ResourceCycles = [3,1];
-} 
+}
 
 // Packed Compare Explicit Length Strings, Return Mask
 def : WriteRes<WritePCmpEStrM, [SKXPort0, SKXPort5, SKXPort015, SKXPort0156]> {
@@ -3918,7 +3918,7 @@ def: InstRW<[SKXWriteResGroup118], (inst
 def SKXWriteResGroup118_16_1 : SchedWriteRes<[SKXPort1, SKXPort0156, SKXPort23]> {
   let Latency = 8;
   let NumMicroOps = 3;
-  let ResourceCycles = [1,1,1]; 
+  let ResourceCycles = [1,1,1];
 }
 def: InstRW<[SKXWriteResGroup118_16_1], (instrs IMUL16rm, IMUL16rmi, IMUL16rmi8)>;
 
@@ -5564,9 +5564,9 @@ def SKXWriteResGroup192_2 : SchedWriteRe
   let NumMicroOps = 3;
   let ResourceCycles = [1,2];
 }
-def: InstRW<[SKXWriteResGroup192_2], (instregex "VPMULLDYrm")>;
-def: InstRW<[SKXWriteResGroup192_2], (instregex "VPMULLDZ256rm(b?)(k?)(z?)")>;
-def: InstRW<[SKXWriteResGroup192_2], (instregex "VPMULLDZrm(b?)(k?)(z?)")>;
+def: InstRW<[SKXWriteResGroup192_2], (instregex "VPMULLDYrm",
+                                                "VPMULLDZ256rm(b?)(k?)(z?)",
+                                                "VPMULLDZrm(b?)(k?)(z?)")>;
 
 def SKXWriteResGroup193 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort015]> {
   let Latency = 15;