[llvm] r328349 - [AMDGPU] Remove use of OpenCL triple environment and replace with function attribute for AMDGPU
Tony Tye via llvm-commits
llvm-commits at lists.llvm.org
Fri Mar 23 11:45:18 PDT 2018
Author: t-tye
Date: Fri Mar 23 11:45:18 2018
New Revision: 328349
URL: http://llvm.org/viewvc/llvm-project?rev=328349&view=rev
Log:
[AMDGPU] Remove use of OpenCL triple environment and replace with function attribute for AMDGPU
- Remove use of the opencl and amdopencl environment member of the target triple for the AMDGPU target.
- Use function attribute to communicate to the AMDGPU backend to add implicit arguments for OpenCL kernels for the AMDHSA OS.
Differential Revision: https://reviews.llvm.org/D43736
Modified:
llvm/trunk/docs/AMDGPUUsage.rst
llvm/trunk/include/llvm/ADT/Triple.h
llvm/trunk/lib/Support/Triple.cpp
llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.h
llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.implicitarg.ptr.ll
llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.kernarg.segment.ptr.ll
llvm/trunk/unittests/ADT/TripleTest.cpp
Modified: llvm/trunk/docs/AMDGPUUsage.rst
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/AMDGPUUsage.rst?rev=328349&r1=328348&r2=328349&view=diff
==============================================================================
--- llvm/trunk/docs/AMDGPUUsage.rst (original)
+++ llvm/trunk/docs/AMDGPUUsage.rst Fri Mar 23 11:45:18 2018
@@ -64,9 +64,7 @@ specify the target triple:
============ ==============================================================
Environment Description
============ ==============================================================
- *<empty>* Defaults to ``opencl``.
- ``opencl`` OpenCL compute kernel (see :ref:`amdgpu-opencl`).
- ``hcc`` AMD HC language compute kernel (see :ref:`amdgpu-hcc`).
+ *<empty>* Default.
============ ==============================================================
.. _amdgpu-processors:
@@ -3787,35 +3785,37 @@ Source Languages
OpenCL
------
-When generating code for the OpenCL language the target triple environment
-should be ``opencl`` or ``amdgizcl`` (see :ref:`amdgpu-target-triples`).
-
When the language is OpenCL the following differences occur:
1. The OpenCL memory model is used (see :ref:`amdgpu-amdhsa-memory-model`).
-2. The AMDGPU backend adds additional arguments to the kernel.
+2. The AMDGPU backend appends additional arguments to the kernel's explicit
+ arguments for the AMDHSA OS (see
+ :ref:`opencl-kernel-implicit-arguments-appended-for-amdhsa-os-table`).
3. Additional metadata is generated
- (:ref:`amdgpu-amdhsa-hsa-code-object-metadata`).
+ (see :ref:`amdgpu-amdhsa-hsa-code-object-metadata`).
-.. TODO
- Specify what affect this has. Hidden arguments added. Additional metadata
- generated.
+ .. table:: OpenCL kernel implicit arguments appended for AMDHSA OS
+ :name: opencl-kernel-implicit-arguments-appended-for-amdhsa-os-table
+
+ ======== ==== ========= ===========================================
+ Position Byte Byte Description
+ Size Alignment
+ ======== ==== ========= ===========================================
+ 0 8 8 OpenCL Global Offset X
+ 1 8 8 OpenCL Global Offset Y
+ 2 8 8 OpenCL Global Offset Z
+ 3 8 8 OpenCL printf buffer
+ ======== ==== ========= ===========================================
.. _amdgpu-hcc:
HCC
---
-When generating code for the OpenCL language the target triple environment
-should be ``hcc`` (see :ref:`amdgpu-target-triples`).
-
-When the language is OpenCL the following differences occur:
+When the language is HCC the following differences occur:
1. The HSA memory model is used (see :ref:`amdgpu-amdhsa-memory-model`).
-.. TODO
- Specify what affect this has.
-
Assembler
---------
Modified: llvm/trunk/include/llvm/ADT/Triple.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/Triple.h?rev=328349&r1=328348&r2=328349&view=diff
==============================================================================
--- llvm/trunk/include/llvm/ADT/Triple.h (original)
+++ llvm/trunk/include/llvm/ADT/Triple.h Fri Mar 23 11:45:18 2018
@@ -203,7 +203,6 @@ public:
Itanium,
Cygnus,
CoreCLR,
- OpenCL,
Simulator, // Simulator variants of other systems, e.g., Apple's iOS
LastEnvironmentType = Simulator
};
Modified: llvm/trunk/lib/Support/Triple.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/Triple.cpp?rev=328349&r1=328348&r2=328349&view=diff
==============================================================================
--- llvm/trunk/lib/Support/Triple.cpp (original)
+++ llvm/trunk/lib/Support/Triple.cpp Fri Mar 23 11:45:18 2018
@@ -233,7 +233,6 @@ StringRef Triple::getEnvironmentTypeName
case Itanium: return "itanium";
case Cygnus: return "cygnus";
case CoreCLR: return "coreclr";
- case OpenCL: return "opencl";
case Simulator: return "simulator";
}
@@ -523,7 +522,6 @@ static Triple::EnvironmentType parseEnvi
.StartsWith("itanium", Triple::Itanium)
.StartsWith("cygnus", Triple::Cygnus)
.StartsWith("coreclr", Triple::CoreCLR)
- .StartsWith("opencl", Triple::OpenCL)
.StartsWith("simulator", Triple::Simulator)
.Default(Triple::UnknownEnvironment);
}
Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.h?rev=328349&r1=328348&r2=328349&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.h (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.h Fri Mar 23 11:45:18 2018
@@ -212,11 +212,6 @@ public:
return TargetTriple.getOS() == Triple::Mesa3D;
}
- bool isOpenCLEnv() const {
- return TargetTriple.getEnvironment() == Triple::OpenCL ||
- TargetTriple.getEnvironmentName() == "amdgizcl";
- }
-
bool isAmdPalOS() const {
return TargetTriple.getOS() == Triple::AMDPAL;
}
@@ -543,12 +538,13 @@ public:
return isAmdHsaOS() ? 8 : 4;
}
+ /// \returns Number of bytes of arguments that are passed to a shader or
+ /// kernel in addition to the explicit ones declared for the function.
unsigned getImplicitArgNumBytes(const MachineFunction &MF) const {
if (isMesaKernel(MF))
return 16;
- if (isAmdHsaOS() && isOpenCLEnv())
- return 32;
- return 0;
+ return AMDGPU::getIntegerAttribute(
+ MF.getFunction(), "amdgpu-implicitarg-num-bytes", 0);
}
// Scratch is allocated in 256 dword per wave blocks for the entire
Modified: llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.implicitarg.ptr.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.implicitarg.ptr.ll?rev=328349&r1=328348&r2=328349&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.implicitarg.ptr.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.implicitarg.ptr.ll Fri Mar 23 11:45:18 2018
@@ -1,12 +1,10 @@
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,HSA,HSA-NOENV %s
-; RUN: llc -mtriple=amdgcn-amd-amdhsa-opencl -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,HSA,HSA-OPENCL %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,HSA %s
; RUN: llc -mtriple=amdgcn-mesa-mesa3d -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,MESA %s
; GCN-LABEL: {{^}}kernel_implicitarg_ptr_empty:
; GCN: enable_sgpr_kernarg_segment_ptr = 1
-; HSA-NOENV: kernarg_segment_byte_size = 0
-; HSA-OPENCL: kernarg_segment_byte_size = 32
+; HSA: kernarg_segment_byte_size = 0
; MESA: kernarg_segment_byte_size = 16
; HSA: s_load_dword s0, s[4:5], 0x0
@@ -17,11 +15,24 @@ define amdgpu_kernel void @kernel_implic
ret void
}
+; GCN-LABEL: {{^}}opencl_kernel_implicitarg_ptr_empty:
+; GCN: enable_sgpr_kernarg_segment_ptr = 1
+
+; HSA: kernarg_segment_byte_size = 32
+; MESA: kernarg_segment_byte_size = 16
+
+; HSA: s_load_dword s0, s[4:5], 0x0
+define amdgpu_kernel void @opencl_kernel_implicitarg_ptr_empty() #1 {
+ %implicitarg.ptr = call i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr()
+ %cast = bitcast i8 addrspace(4)* %implicitarg.ptr to i32 addrspace(4)*
+ %load = load volatile i32, i32 addrspace(4)* %cast
+ ret void
+}
+
; GCN-LABEL: {{^}}kernel_implicitarg_ptr:
; GCN: enable_sgpr_kernarg_segment_ptr = 1
-; HSA-NOENV: kernarg_segment_byte_size = 112
-; HSA-OPENCL: kernarg_segment_byte_size = 144
+; HSA: kernarg_segment_byte_size = 112
; MESA: kernarg_segment_byte_size = 464
; HSA: s_load_dword s0, s[4:5], 0x1c
@@ -32,6 +43,20 @@ define amdgpu_kernel void @kernel_implic
ret void
}
+; GCN-LABEL: {{^}}opencl_kernel_implicitarg_ptr:
+; GCN: enable_sgpr_kernarg_segment_ptr = 1
+
+; HSA: kernarg_segment_byte_size = 144
+; MESA: kernarg_segment_byte_size = 464
+
+; HSA: s_load_dword s0, s[4:5], 0x1c
+define amdgpu_kernel void @opencl_kernel_implicitarg_ptr([112 x i8]) #1 {
+ %implicitarg.ptr = call i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr()
+ %cast = bitcast i8 addrspace(4)* %implicitarg.ptr to i32 addrspace(4)*
+ %load = load volatile i32, i32 addrspace(4)* %cast
+ ret void
+}
+
; GCN-LABEL: {{^}}func_implicitarg_ptr:
; GCN: s_waitcnt
; MESA: s_mov_b64 s[8:9], s[6:7]
@@ -43,7 +68,25 @@ define amdgpu_kernel void @kernel_implic
; HSA: flat_load_dword v0, v[0:1]
; GCN-NEXT: s_waitcnt
; GCN-NEXT: s_setpc_b64
-define void @func_implicitarg_ptr() #1 {
+define void @func_implicitarg_ptr() #0 {
+ %implicitarg.ptr = call i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr()
+ %cast = bitcast i8 addrspace(4)* %implicitarg.ptr to i32 addrspace(4)*
+ %load = load volatile i32, i32 addrspace(4)* %cast
+ ret void
+}
+
+; GCN-LABEL: {{^}}opencl_func_implicitarg_ptr:
+; GCN: s_waitcnt
+; MESA: s_mov_b64 s[8:9], s[6:7]
+; MESA: s_mov_b32 s11, 0xf000
+; MESA: s_mov_b32 s10, -1
+; MESA: buffer_load_dword v0, off, s[8:11], 0
+; HSA: v_mov_b32_e32 v0, s6
+; HSA: v_mov_b32_e32 v1, s7
+; HSA: flat_load_dword v0, v[0:1]
+; GCN-NEXT: s_waitcnt
+; GCN-NEXT: s_setpc_b64
+define void @opencl_func_implicitarg_ptr() #0 {
%implicitarg.ptr = call i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr()
%cast = bitcast i8 addrspace(4)* %implicitarg.ptr to i32 addrspace(4)*
%load = load volatile i32, i32 addrspace(4)* %cast
@@ -52,8 +95,7 @@ define void @func_implicitarg_ptr() #1 {
; GCN-LABEL: {{^}}kernel_call_implicitarg_ptr_func_empty:
; GCN: enable_sgpr_kernarg_segment_ptr = 1
-; HSA-NOENV: kernarg_segment_byte_size = 0
-; HSA-OPENCL: kernarg_segment_byte_size = 32
+; HSA: kernarg_segment_byte_size = 0
; MESA: kernarg_segment_byte_size = 16
; GCN: s_mov_b64 s[6:7], s[4:5]
; GCN: s_swappc_b64
@@ -62,10 +104,20 @@ define amdgpu_kernel void @kernel_call_i
ret void
}
+; GCN-LABEL: {{^}}opencl_kernel_call_implicitarg_ptr_func_empty:
+; GCN: enable_sgpr_kernarg_segment_ptr = 1
+; HSA: kernarg_segment_byte_size = 32
+; MESA: kernarg_segment_byte_size = 16
+; GCN: s_mov_b64 s[6:7], s[4:5]
+; GCN: s_swappc_b64
+define amdgpu_kernel void @opencl_kernel_call_implicitarg_ptr_func_empty() #1 {
+ call void @func_implicitarg_ptr()
+ ret void
+}
+
; GCN-LABEL: {{^}}kernel_call_implicitarg_ptr_func:
; GCN: enable_sgpr_kernarg_segment_ptr = 1
-; HSA-OPENCL: kernarg_segment_byte_size = 144
-; HSA-NOENV: kernarg_segment_byte_size = 112
+; HSA: kernarg_segment_byte_size = 112
; MESA: kernarg_segment_byte_size = 464
; HSA: s_add_u32 s6, s4, 0x70
@@ -78,11 +130,35 @@ define amdgpu_kernel void @kernel_call_i
ret void
}
+; GCN-LABEL: {{^}}opencl_kernel_call_implicitarg_ptr_func:
+; GCN: enable_sgpr_kernarg_segment_ptr = 1
+; HSA: kernarg_segment_byte_size = 144
+; MESA: kernarg_segment_byte_size = 464
+
+; HSA: s_add_u32 s6, s4, 0x70
+; MESA: s_add_u32 s6, s4, 0x1c0
+
+; GCN: s_addc_u32 s7, s5, 0{{$}}
+; GCN: s_swappc_b64
+define amdgpu_kernel void @opencl_kernel_call_implicitarg_ptr_func([112 x i8]) #1 {
+ call void @func_implicitarg_ptr()
+ ret void
+}
+
; GCN-LABEL: {{^}}func_call_implicitarg_ptr_func:
; GCN-NOT: s6
; GCN-NOT: s7
; GCN-NOT: s[6:7]
-define void @func_call_implicitarg_ptr_func() #1 {
+define void @func_call_implicitarg_ptr_func() #0 {
+ call void @func_implicitarg_ptr()
+ ret void
+}
+
+; GCN-LABEL: {{^}}opencl_func_call_implicitarg_ptr_func:
+; GCN-NOT: s6
+; GCN-NOT: s7
+; GCN-NOT: s[6:7]
+define void @opencl_func_call_implicitarg_ptr_func() #0 {
call void @func_implicitarg_ptr()
ret void
}
@@ -104,7 +180,34 @@ define void @func_call_implicitarg_ptr_f
; HSA: flat_load_dword v0, v[0:1]
; GCN: s_waitcnt vmcnt(0)
-define void @func_kernarg_implicitarg_ptr() #1 {
+define void @func_kernarg_implicitarg_ptr() #0 {
+ %kernarg.segment.ptr = call i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr()
+ %implicitarg.ptr = call i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr()
+ %cast.kernarg.segment.ptr = bitcast i8 addrspace(4)* %kernarg.segment.ptr to i32 addrspace(4)*
+ %cast.implicitarg = bitcast i8 addrspace(4)* %implicitarg.ptr to i32 addrspace(4)*
+ %load0 = load volatile i32, i32 addrspace(4)* %cast.kernarg.segment.ptr
+ %load1 = load volatile i32, i32 addrspace(4)* %cast.implicitarg
+ ret void
+}
+
+; GCN-LABEL: {{^}}opencl_func_kernarg_implicitarg_ptr:
+; GCN: s_waitcnt
+; MESA: s_mov_b64 s[12:13], s[6:7]
+; MESA: s_mov_b32 s15, 0xf000
+; MESA: s_mov_b32 s14, -1
+; MESA: buffer_load_dword v0, off, s[12:15], 0
+; HSA: v_mov_b32_e32 v0, s6
+; HSA: v_mov_b32_e32 v1, s7
+; HSA: flat_load_dword v0, v[0:1]
+; MESA: s_mov_b32 s10, s14
+; MESA: s_mov_b32 s11, s15
+; MESA: buffer_load_dword v0, off, s[8:11], 0
+; HSA: v_mov_b32_e32 v0, s8
+; HSA: v_mov_b32_e32 v1, s9
+; HSA: flat_load_dword v0, v[0:1]
+
+; GCN: s_waitcnt vmcnt(0)
+define void @opencl_func_kernarg_implicitarg_ptr() #0 {
%kernarg.segment.ptr = call i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr()
%implicitarg.ptr = call i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr()
%cast.kernarg.segment.ptr = bitcast i8 addrspace(4)* %kernarg.segment.ptr to i32 addrspace(4)*
@@ -129,5 +232,5 @@ declare i8 addrspace(4)* @llvm.amdgcn.im
declare i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr() #2
attributes #0 = { nounwind noinline }
-attributes #1 = { nounwind noinline }
+attributes #1 = { nounwind noinline "amdgpu-implicitarg-num-bytes"="32" }
attributes #2 = { nounwind readnone speculatable }
Modified: llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.kernarg.segment.ptr.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.kernarg.segment.ptr.ll?rev=328349&r1=328348&r2=328349&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.kernarg.segment.ptr.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.kernarg.segment.ptr.ll Fri Mar 23 11:45:18 2018
@@ -1,9 +1,6 @@
-; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefixes=CO-V2,HSA,ALL,HSA-NOENV %s
-; RUN: llc -mtriple=amdgcn--amdhsa-opencl -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefixes=CO-V2,HSA,ALL,HSA-OPENCL %s
+; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefixes=CO-V2,HSA,ALL %s
; RUN: llc -mtriple=amdgcn-mesa-mesa3d -verify-machineinstrs < %s | FileCheck -check-prefixes=CO-V2,OS-MESA3D,MESA,ALL %s
; RUN: llc -mtriple=amdgcn-mesa-unknown -verify-machineinstrs < %s | FileCheck -check-prefixes=OS-UNKNOWN,MESA,ALL %s
-; RUN: llc -mtriple=amdgcn--amdhsa-amdgiz -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefixes=CO-V2,HSA,ALL,HSA-NOENV %s
-; RUN: llc -mtriple=amdgcn--amdhsa-amdgizcl -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefixes=CO-V2,HSA,ALL,HSA-OPENCL %s
; ALL-LABEL: {{^}}test:
; CO-V2: enable_sgpr_kernarg_segment_ptr = 1
@@ -32,8 +29,7 @@ define amdgpu_kernel void @test_implicit
}
; ALL-LABEL: {{^}}test_implicit_alignment
-; HSA-NOENV: kernarg_segment_byte_size = 10
-; HSA-OPENCL: kernarg_segment_byte_size = 48
+; HSA: kernarg_segment_byte_size = 10
; OS-MESA3D: kernarg_segment_byte_size = 28
; OS-UNKNOWN: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0xc
; HSA: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x4
@@ -49,6 +45,23 @@ define amdgpu_kernel void @test_implicit
ret void
}
+; ALL-LABEL: {{^}}opencl_test_implicit_alignment
+; HSA: kernarg_segment_byte_size = 48
+; OS-MESA3D: kernarg_segment_byte_size = 28
+; OS-UNKNOWN: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0xc
+; HSA: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x4
+; OS-MESA3D: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x3
+; ALL: v_mov_b32_e32 [[V_VAL:v[0-9]+]], [[VAL]]
+; MESA: buffer_store_dword [[V_VAL]]
+; HSA: flat_store_dword v[{{[0-9]+:[0-9]+}}], [[V_VAL]]
+define amdgpu_kernel void @opencl_test_implicit_alignment(i32 addrspace(1)* %out, <2 x i8> %in) #2 {
+ %implicitarg.ptr = call noalias i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr()
+ %arg.ptr = bitcast i8 addrspace(4)* %implicitarg.ptr to i32 addrspace(4)*
+ %val = load i32, i32 addrspace(4)* %arg.ptr
+ store i32 %val, i32 addrspace(1)* %out
+ ret void
+}
+
; ALL-LABEL: {{^}}test_no_kernargs:
; HSA: enable_sgpr_kernarg_segment_ptr = 1
; HSA: s_load_dword s{{[0-9]+}}, s[4:5]
@@ -66,3 +79,4 @@ declare i8 addrspace(4)* @llvm.amdgcn.im
attributes #0 = { nounwind readnone }
attributes #1 = { nounwind }
+attributes #2 = { nounwind "amdgpu-implicitarg-num-bytes"="32" }
Modified: llvm/trunk/unittests/ADT/TripleTest.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/unittests/ADT/TripleTest.cpp?rev=328349&r1=328348&r2=328349&view=diff
==============================================================================
--- llvm/trunk/unittests/ADT/TripleTest.cpp (original)
+++ llvm/trunk/unittests/ADT/TripleTest.cpp Fri Mar 23 11:45:18 2018
@@ -283,12 +283,6 @@ TEST(TripleTest, ParsedIDs) {
EXPECT_EQ(Triple::AMDHSA, T.getOS());
EXPECT_EQ(Triple::UnknownEnvironment, T.getEnvironment());
- T = Triple("amdgcn-amd-amdhsa-opencl");
- EXPECT_EQ(Triple::amdgcn, T.getArch());
- EXPECT_EQ(Triple::AMD, T.getVendor());
- EXPECT_EQ(Triple::AMDHSA, T.getOS());
- EXPECT_EQ(Triple::OpenCL, T.getEnvironment());
-
T = Triple("amdgcn-amd-amdpal");
EXPECT_EQ(Triple::amdgcn, T.getArch());
EXPECT_EQ(Triple::AMD, T.getVendor());
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