[PATCH] D44840: [X86] Add the ability to override memory folding latency to schedules and add 1uop for memory folds to Intel models

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon created this revision.
RKSimon added reviewers: craig.topper, courbet, spatel, andreadb.

The Intel models need an extra 1uop for memory folded instructions, plus a lot of instruction take a non-default memory latency which should allow us to use the multiclass a lot more to tidy things up.


Repository:
  rL LLVM

https://reviews.llvm.org/D44840

Files:
  lib/Target/X86/X86SchedBroadwell.td
  lib/Target/X86/X86SchedHaswell.td
  lib/Target/X86/X86SchedSandyBridge.td
  lib/Target/X86/X86SchedSkylakeClient.td
  lib/Target/X86/X86SchedSkylakeServer.td
  lib/Target/X86/X86ScheduleSLM.td

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