[llvm] r328290 - [X86] Add VEXTRB/W/D/Q to Zen scheduler model.

[Craig Topper via llvm-commits]

Author: ctopper
Date: Thu Mar 22 23:41:36 2018
New Revision: 328290

URL: http://llvm.org/viewvc/llvm-project?rev=328290&view=rev
Log:
[X86] Add VEXTRB/W/D/Q to Zen scheduler model.

The SSE versions were present, but not the VEX version.

Modified:
    llvm/trunk/lib/Target/X86/X86ScheduleZnver1.td
    llvm/trunk/test/CodeGen/X86/sse-schedule.ll
    llvm/trunk/test/CodeGen/X86/sse2-schedule.ll
    llvm/trunk/test/CodeGen/X86/sse41-schedule.ll

Modified: llvm/trunk/lib/Target/X86/X86ScheduleZnver1.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ScheduleZnver1.td?rev=328290&r1=328289&r2=328290&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ScheduleZnver1.td (original)
+++ llvm/trunk/lib/Target/X86/X86ScheduleZnver1.td Thu Mar 22 23:41:36 2018
@@ -1033,7 +1033,7 @@ def ZnWritePEXTRr : SchedWriteRes<[ZnFPU
   let Latency = 2;
   let ResourceCycles = [1, 2];
 }
-def : InstRW<[ZnWritePEXTRr], (instregex "PEXTR(B|W|D|Q)rr", "MMX_PEXTRWrr")>;
+def : InstRW<[ZnWritePEXTRr], (instregex "(V?)PEXTR(B|W|D|Q)rr", "MMX_PEXTRWrr")>;
 
 def ZnWritePEXTRm : SchedWriteRes<[ZnAGU, ZnFPU12, ZnFPU2]> {
   let Latency = 5;
@@ -1041,7 +1041,7 @@ def ZnWritePEXTRm : SchedWriteRes<[ZnAGU
   let ResourceCycles = [1, 2, 3];
 }
 // m8,x,i.
-def : InstRW<[ZnWritePEXTRm], (instregex "PEXTR(B|W|D|Q)mr")>;
+def : InstRW<[ZnWritePEXTRm], (instregex "(V?)PEXTR(B|W|D|Q)mr")>;
 
 // VPBROADCAST B/W.
 // x, m8/16.

Modified: llvm/trunk/test/CodeGen/X86/sse-schedule.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse-schedule.ll?rev=328290&r1=328289&r2=328290&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/sse-schedule.ll (original)
+++ llvm/trunk/test/CodeGen/X86/sse-schedule.ll Thu Mar 22 23:41:36 2018
@@ -1738,7 +1738,7 @@ define void @test_movhps(<4 x float> %a0
 ; ZNVER1:       # %bb.0:
 ; ZNVER1-NEXT:    vmovhpd {{.*#+}} xmm1 = xmm1[0],mem[0] sched: [8:0.50]
 ; ZNVER1-NEXT:    vaddps %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
-; ZNVER1-NEXT:    vpextrq $1, %xmm0, (%rdi) # sched: [8:1.00]
+; ZNVER1-NEXT:    vpextrq $1, %xmm0, (%rdi) # sched: [5:3.00]
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   %1 = bitcast x86_mmx* %a2 to <2 x float>*
   %2 = load <2 x float>, <2 x float> *%1, align 8

Modified: llvm/trunk/test/CodeGen/X86/sse2-schedule.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse2-schedule.ll?rev=328290&r1=328289&r2=328290&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/sse2-schedule.ll (original)
+++ llvm/trunk/test/CodeGen/X86/sse2-schedule.ll Thu Mar 22 23:41:36 2018
@@ -5538,7 +5538,7 @@ define i16 @test_pextrw(<8 x i16> %a0) {
 ;
 ; ZNVER1-LABEL: test_pextrw:
 ; ZNVER1:       # %bb.0:
-; ZNVER1-NEXT:    vpextrw $6, %xmm0, %eax # sched: [1:0.25]
+; ZNVER1-NEXT:    vpextrw $6, %xmm0, %eax # sched: [2:2.00]
 ; ZNVER1-NEXT:    # kill: def $ax killed $ax killed $eax
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   %1 = extractelement <8 x i16> %a0, i32 6

Modified: llvm/trunk/test/CodeGen/X86/sse41-schedule.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse41-schedule.ll?rev=328290&r1=328289&r2=328290&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/sse41-schedule.ll (original)
+++ llvm/trunk/test/CodeGen/X86/sse41-schedule.ll Thu Mar 22 23:41:36 2018
@@ -954,8 +954,8 @@ define i32 @test_pextrb(<16 x i8> %a0, i
 ;
 ; ZNVER1-LABEL: test_pextrb:
 ; ZNVER1:       # %bb.0:
-; ZNVER1-NEXT:    vpextrb $3, %xmm0, %eax # sched: [1:0.25]
-; ZNVER1-NEXT:    vpextrb $1, %xmm0, (%rdi) # sched: [8:1.00]
+; ZNVER1-NEXT:    vpextrb $3, %xmm0, %eax # sched: [2:2.00]
+; ZNVER1-NEXT:    vpextrb $1, %xmm0, (%rdi) # sched: [5:3.00]
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   %1 = extractelement <16 x i8> %a0, i32 3
   %2 = extractelement <16 x i8> %a0, i32 1
@@ -1024,8 +1024,8 @@ define i32 @test_pextrd(<4 x i32> %a0, i
 ; ZNVER1-LABEL: test_pextrd:
 ; ZNVER1:       # %bb.0:
 ; ZNVER1-NEXT:    vpaddd %xmm0, %xmm0, %xmm0 # sched: [1:0.25]
-; ZNVER1-NEXT:    vpextrd $3, %xmm0, %eax # sched: [1:0.25]
-; ZNVER1-NEXT:    vpextrd $1, %xmm0, (%rdi) # sched: [8:1.00]
+; ZNVER1-NEXT:    vpextrd $3, %xmm0, %eax # sched: [2:2.00]
+; ZNVER1-NEXT:    vpextrd $1, %xmm0, (%rdi) # sched: [5:3.00]
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   %1 = add <4 x i32> %a0, %a0
   %2 = extractelement <4 x i32> %1, i32 3
@@ -1085,8 +1085,8 @@ define i64 @test_pextrq(<2 x i64> %a0, <
 ;
 ; ZNVER1-LABEL: test_pextrq:
 ; ZNVER1:       # %bb.0:
-; ZNVER1-NEXT:    vpextrq $1, %xmm0, %rax # sched: [1:0.25]
-; ZNVER1-NEXT:    vpextrq $1, %xmm0, (%rdi) # sched: [8:1.00]
+; ZNVER1-NEXT:    vpextrq $1, %xmm0, %rax # sched: [2:2.00]
+; ZNVER1-NEXT:    vpextrq $1, %xmm0, (%rdi) # sched: [5:3.00]
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   %1 = extractelement <2 x i64> %a0, i32 1
   %2 = extractelement <2 x i64> %a0, i32 1
@@ -1145,8 +1145,8 @@ define i32 @test_pextrw(<8 x i16> %a0, i
 ;
 ; ZNVER1-LABEL: test_pextrw:
 ; ZNVER1:       # %bb.0:
-; ZNVER1-NEXT:    vpextrw $3, %xmm0, %eax # sched: [1:0.25]
-; ZNVER1-NEXT:    vpextrw $1, %xmm0, (%rdi) # sched: [8:1.00]
+; ZNVER1-NEXT:    vpextrw $3, %xmm0, %eax # sched: [2:2.00]
+; ZNVER1-NEXT:    vpextrw $1, %xmm0, (%rdi) # sched: [5:3.00]
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   %1 = extractelement <8 x i16> %a0, i32 3
   %2 = extractelement <8 x i16> %a0, i32 1