[PATCH] D44654: [X86][SandyBridge] SBWriteResPair +5cy and +1uop Memory Folds

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon updated this revision to Diff 139146.
RKSimon added a comment.

Fixed comment and rebased patch.

Another issue is WriteLoad is set to 4cy but WriteFLoad/WriteVecLoad is set to 6cy memory latency - there are a lot of inconsistencies in here.

I'm open to any/all recommendations - plus I think we need to bear in mind that this model is used for generic (non-specific) x86_64 targets.


Repository:
  rL LLVM

https://reviews.llvm.org/D44654

Files:
  lib/Target/X86/X86SchedSandyBridge.td
  test/CodeGen/X86/3dnow-schedule.ll
  test/CodeGen/X86/adx-schedule.ll
  test/CodeGen/X86/avx-schedule.ll
  test/CodeGen/X86/avx2-schedule.ll
  test/CodeGen/X86/avx512-schedule.ll
  test/CodeGen/X86/avx512-shuffle-schedule.ll
  test/CodeGen/X86/avx512vpopcntdq-schedule.ll
  test/CodeGen/X86/bmi-schedule.ll
  test/CodeGen/X86/bmi2-schedule.ll
  test/CodeGen/X86/f16c-schedule.ll
  test/CodeGen/X86/fma-schedule.ll
  test/CodeGen/X86/fma4-schedule.ll
  test/CodeGen/X86/lzcnt-schedule.ll
  test/CodeGen/X86/mmx-schedule.ll
  test/CodeGen/X86/movbe-schedule.ll
  test/CodeGen/X86/schedule-x86_32.ll
  test/CodeGen/X86/schedule-x86_64.ll
  test/CodeGen/X86/sha-schedule.ll
  test/CodeGen/X86/sse2-schedule.ll
  test/CodeGen/X86/sse41-schedule.ll
  test/CodeGen/X86/sse42-schedule.ll
  test/CodeGen/X86/tbm-schedule.ll
  test/CodeGen/X86/x87-schedule.ll
  test/CodeGen/X86/xop-schedule.ll