[llvm] r327651 - [PPC] Avoid non-simple MVT in STBRX optimization

[Guozhi Wei via llvm-commits]

Author: carrot
Date: Thu Mar 15 10:49:12 2018
New Revision: 327651

URL: http://llvm.org/viewvc/llvm-project?rev=327651&view=rev
Log:
[PPC] Avoid non-simple MVT in STBRX optimization

PR35402 triggered this case. It bswap and stores a 48bit value, current STBRX optimization transforms it into STBRX. Unfortunately 48bit is not a simple MVT, there is no PPC instruction to support it, and it can't be automatically expanded by llvm, so caused a crash.

This patch detects the non-simple MVT and returns early.

Differential Revision: https://reviews.llvm.org/D44500


Added:
    llvm/trunk/test/CodeGen/PowerPC/pr35402.ll
Modified:
    llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp

Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=327651&r1=327650&r2=327651&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Thu Mar 15 10:49:12 2018
@@ -12285,6 +12285,11 @@ SDValue PPCTargetLowering::PerformDAGCom
          N->getOperand(1).getValueType() == MVT::i16 ||
          (Subtarget.hasLDBRX() && Subtarget.isPPC64() &&
           N->getOperand(1).getValueType() == MVT::i64))) {
+      // STBRX can only handle simple types.
+      EVT mVT = cast<StoreSDNode>(N)->getMemoryVT();
+      if (mVT.isExtended())
+        break;
+
       SDValue BSwapOp = N->getOperand(1).getOperand(0);
       // Do an any-extend to 32-bits if this is a half-word input.
       if (BSwapOp.getValueType() == MVT::i16)
@@ -12292,7 +12297,6 @@ SDValue PPCTargetLowering::PerformDAGCom
 
       // If the type of BSWAP operand is wider than stored memory width
       // it need to be shifted to the right side before STBRX.
-      EVT mVT = cast<StoreSDNode>(N)->getMemoryVT();
       if (Op1VT.bitsGT(mVT)) {
         int Shift = Op1VT.getSizeInBits() - mVT.getSizeInBits();
         BSwapOp = DAG.getNode(ISD::SRL, dl, Op1VT, BSwapOp,

Added: llvm/trunk/test/CodeGen/PowerPC/pr35402.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/pr35402.ll?rev=327651&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/pr35402.ll (added)
+++ llvm/trunk/test/CodeGen/PowerPC/pr35402.ll Thu Mar 15 10:49:12 2018
@@ -0,0 +1,18 @@
+; RUN: llc -O2 < %s | FileCheck %s
+target triple = "powerpc64le-linux-gnu"
+
+define void @test(i8* %p, i64 %data) {
+entry:
+  %0 = tail call i64 @llvm.bswap.i64(i64 %data)
+  %ptr = bitcast i8* %p to i48*
+  %val = trunc i64 %0 to i48
+  store i48 %val, i48* %ptr, align 1
+  ret void
+
+; CHECK:     sth
+; CHECK:     stw
+; CHECK-NOT: stdbrx
+
+}
+
+declare i64 @llvm.bswap.i64(i64)