[PATCH] D44370: [X86] Combine vXi64 multiplies to MULDQ/MULUDQ during DAG combine instead of lowering.

[Craig Topper via Phabricator via llvm-commits]

craig.topper updated this revision to Diff 138112.
craig.topper added a comment.

Added a flag to SplitBinaryOpsAndApply to control checking useBWIRegs or useAVX512Regs. I wanted to do it based on VT, but PMADDWD uses a vXi32 result VT and a vXi16 input VT.

Also removed some more code from LowerMUL that checked for hasDQI.


Repository:
  rL LLVM

https://reviews.llvm.org/D44370

Files:
  lib/Target/X86/X86ISelLowering.cpp
  test/CodeGen/X86/mulvi32.ll

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