[PATCH] D43971: [AArch64] Implement native TLS for Windows

[Martin Storsjö via Phabricator via llvm-commits]

mstorsjo added a comment.

In https://reviews.llvm.org/D43971#1032589, @rengolin wrote:

> In https://reviews.llvm.org/D43971#1031818, @mstorsjo wrote:
>
> > First: Currently there's the pseudoinstruction LOADgot which lowers into a "adrp + ldr" instruction pair, but the ldr always loads a full X-register. Here I needed to do that, but load a W-register instead, to only read 32 bits. I tried to do this by adding a separate LOADgot32 pseudoinstruction, but I wasn't able to make it return a 32 bit value on the SelectionDAG level.
>
>
> Maybe the functionality was lost for not being tested properly on Windows?


No, that's probably because it aarch64-windows didn't exist at all back then (there's even no publicly available hardware yet), so this just did something else (looks like ELF relocations). And the issue isn't with reading tls vars of different sizes, but just in one small piece of implementing it properly - when reading the global `_tls_index` variable, which is a 32 bit value.

To reproduce the issue with this, that I'm facing, try adding the following to `AArch64InstrInfo.td` (next to the existing similar pattern for LOADgot):

  def LOADgot32 : Pseudo<(outs GPR32:$dst), (ins i64imm:$addr),
                       [(set GPR32:$dst, (AArch64LOADgot tglobaladdr:$addr))]>,
                Sched<[WriteLDAdr]>;

When building with this pattern in place, tablegen fails like this:

  FAILED: cd /home/martin/code/llvm/build/lib/Target/AArch64 && /home/martin/code/llvm/build/bin/llvm-tblgen -gen-instr-info -I /home/martin/code/llvm/lib/Target/AArch64 -I /home/martin/code/llvm/include -I /home/martin/code/llvm/lib/Target /home/martin/code/llvm/lib/Target/AArch64/AArch64.td -o /home/martin/code/llvm/build/lib/Target/AArch64/AArch64GenInstrInfo.inc.tmp
  Type set is empty for each HW mode:
  possible type contradiction in the pattern below (use -print-records with llvm-tblgen to see all expanded records).
  LOADgot32:      (LOADgot32:{ *:[i32] } (tglobaladdr:{ *:[] }):$addr)
  UNREACHABLE executed at ../utils/TableGen/CodeGenDAGPatterns.cpp:817!

I guess I could try to see what dag nodes this produces if I do such a load of a 32 bit global variable from normal IR.


Repository:
  rL LLVM

https://reviews.llvm.org/D43971