[PATCH] D43971: [AArch64] Implement native TLS for Windows

[Renato Golin via Phabricator via llvm-commits]

rengolin added a comment.

In https://reviews.llvm.org/D43971#1031818, @mstorsjo wrote:

> First: Currently there's the pseudoinstruction LOADgot which lowers into a "adrp + ldr" instruction pair, but the ldr always loads a full X-register. Here I needed to do that, but load a W-register instead, to only read 32 bits. I tried to do this by adding a separate LOADgot32 pseudoinstruction, but I wasn't able to make it return a 32 bit value on the SelectionDAG level.


Right, I see. This seems to be a new problem. When trying it on current trunk, I do get an unreachable, but when I try on older versions (ex. 3.8) I see a much simpler code coming out.

  @tlsVar16 = thread_local global i16 0
  @tlsVar32 = thread_local global i32 0
  @tlsVar64 = thread_local global i64 0
  
  define i64 @getVar() {
    %1 = load i16, i16* @tlsVar16
    %2 = load i32, i32* @tlsVar32
    %3 = load i64, i64* @tlsVar64
  
    %4 = zext i16 %1 to i32
    %5 = add i32 %2, %4
  
    %6 = zext i32 %5 to i64
    %7 = add i64 %3, %6
    ret i64 %7
  }

then:

  $ llc -mtriple aarch64-windows tls-32b.ll -o -

I get:

  mrs  x8, TPIDR_EL0
  add  x9, x8, :tprel_hi12:tlsVar16
  add  x10, x8, :tprel_hi12:tlsVar32
  add  x8, x8, :tprel_hi12:tlsVar64
  add  x9, x9, :tprel_lo12_nc:tlsVar16
  add  x10, x10, :tprel_lo12_nc:tlsVar32
  add  x8, x8, :tprel_lo12_nc:tlsVar64
  ldr  w10, [x10]
  ldrh w9, [x9]
  ldr  x8, [x8]
  add  w9, w10, w9
  add  x0, x8, w9, uxtw
  ret

Which does the correct loads for half, single and double sizes.

Maybe the functionality was lost for not being tested properly on Windows?

> Secondly: When I do a series of SHL + ZERO_EXTEND + Load, I would want it lowered into a `ldr x0, [x0, w1 uxtw #3]`, but it ends up as `lsl w1, w1, #3; ldr x0, [x0, w1 uxtw]` which feels pointless. I remember doing similar things elsewhere, where it was folded properly into the ldr as a shift - what's missing here?
> 
> Who's familiar with the tablegen part of the AArch64 backend and/or SelectionDAG and can help out with this?

AFAICR, this is supposed to be done by the DAGCombine. However, it depends on when the Pseudos get expanded (I forget). If it's too late, then they won't get merged.


Repository:
  rL LLVM

https://reviews.llvm.org/D43971