[PATCH] D43620: [Pipeliner] Fixed node order issue related to zero latency edges

[Krzysztof Parzyszek via Phabricator via llvm-commits]

kparzysz added a comment.

This change causes some issues.  The following testcase crashes or runs until memory is exhausted.

  define void @f0(i32 %a0) #0 {
  b0:
    %v0 = ashr i32 %a0, 1
    br label %b1
  
  b1:                                               ; preds = %b1, %b0
    %v1 = phi i64 [ %v7, %b1 ], [ 0, %b0 ]
    %v2 = phi i64 [ %v6, %b1 ], [ undef, %b0 ]
    %v3 = phi i64 [ %v8, %b1 ], [ undef, %b0 ]
    %v4 = phi i32 [ %v9, %b1 ], [ 0, %b0 ]
    %v5 = tail call i64 @llvm.hexagon.S2.shuffeh(i64 undef, i64 %v2)
    %v6 = tail call i64 @llvm.hexagon.A2.combinew(i32 undef, i32 undef)
    %v7 = tail call i64 @llvm.hexagon.M2.vdmacs.s0(i64 %v1, i64 %v3, i64 %v5)
    %v8 = tail call i64 @llvm.hexagon.A2.combinew(i32 undef, i32 undef)
    %v9 = add nsw i32 %v4, 1
    %v10 = icmp eq i32 %v9, %v0
    br i1 %v10, label %b2, label %b1
  
  b2:                                               ; preds = %b1
    %v11 = trunc i64 %v7 to i32
    %v12 = bitcast i8* undef to i32*
    store i32 %v11, i32* %v12, align 4, !tbaa !0
    call void @llvm.trap()
    unreachable
  }
  
  declare i64 @llvm.hexagon.A2.combinew(i32, i32) #1
  declare i64 @llvm.hexagon.M2.vdmacs.s0(i64, i64, i64) #1
  declare i64 @llvm.hexagon.S2.shuffeh(i64, i64) #1
  declare void @llvm.trap() #2
  
  attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length64b" }
  attributes #1 = { nounwind readnone }
  attributes #2 = { noreturn nounwind }
  
  !0 = !{!1, !1, i64 0}
  !1 = !{!"int", !2}
  !2 = !{!"omnipotent char", !3}
  !3 = !{!"Simple C/C++ TBAA"}

Run with `llc -march=hexagon`.


Repository:
  rL LLVM

https://reviews.llvm.org/D43620