[llvm] r326826 - [X86] Reject registers that require a REX prefix in inline asm constraints in 32-bit mode

[Craig Topper via llvm-commits]

Author: ctopper
Date: Tue Mar  6 10:56:33 2018
New Revision: 326826

URL: http://llvm.org/viewvc/llvm-project?rev=326826&view=rev
Log:
[X86] Reject registers that require a REX prefix in inline asm constraints in 32-bit mode

We don't currently reject r8-r15 or xmm8-32 or bpl/spl/sil/dil in 32-bit mode.

Differential Revision: https://reviews.llvm.org/D44031

Added:
    llvm/trunk/test/CodeGen/X86/asm-reject-rex.ll
Modified:
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
    llvm/trunk/test/CodeGen/X86/asm-reject-xmm16.ll

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=326826&r1=326825&r2=326826&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Tue Mar  6 10:56:33 2018
@@ -39277,6 +39277,16 @@ X86TargetLowering::getRegForInlineAsmCon
     return Res;
   }
 
+  // Make sure it isn't a register that requires 64-bit mode.
+  if (!Subtarget.is64Bit() &&
+      (isFRClass(*Res.second) || isGRClass(*Res.second)) &&
+      TRI->getEncodingValue(Res.first) >= 8) {
+    // Register requires REX prefix, but we're in 32-bit mode.
+    Res.first = 0;
+    Res.second = nullptr;
+    return Res;
+  }
+
   // Make sure it isn't a register that requires AVX512.
   if (!Subtarget.hasAVX512() && isFRClass(*Res.second) &&
       TRI->getEncodingValue(Res.first) & 0x10) {

Added: llvm/trunk/test/CodeGen/X86/asm-reject-rex.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/asm-reject-rex.ll?rev=326826&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/asm-reject-rex.ll (added)
+++ llvm/trunk/test/CodeGen/X86/asm-reject-rex.ll Tue Mar  6 10:56:33 2018
@@ -0,0 +1,21 @@
+; RUN: not llc -o /dev/null %s -mtriple=i386-unknown-unknown 2>&1 | FileCheck %s
+; Make sure X32 still works.
+; RUN: llc -o /dev/null %s -mtriple=x86_64-linux-gnux32
+
+; CHECK: error: couldn't allocate output register for constraint '{xmm8}'
+define i64 @blup() {
+  %v = tail call i64 asm "", "={xmm8},0"(i64 0)
+  ret i64 %v
+}
+
+; CHECK: error: couldn't allocate output register for constraint '{r8d}'
+define i32 @foo() {
+  %v = tail call i32 asm "", "={r8d},0"(i32 0)
+  ret i32 %v
+}
+
+; CHECK: error: couldn't allocate output register for constraint '{rax}'
+define i64 @bar() {
+  %v = tail call i64 asm "", "={rax},0"(i64 0)
+  ret i64 %v
+}

Modified: llvm/trunk/test/CodeGen/X86/asm-reject-xmm16.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/asm-reject-xmm16.ll?rev=326826&r1=326825&r2=326826&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/asm-reject-xmm16.ll (original)
+++ llvm/trunk/test/CodeGen/X86/asm-reject-xmm16.ll Tue Mar  6 10:56:33 2018
@@ -1,5 +1,5 @@
-; RUN: not llc -o /dev/null %s 2>&1 | FileCheck %s
-target triple = "x86_64--"
+; RUN: not llc -o /dev/null %s -mtriple=x86_64-unknown-unknown 2>&1 | FileCheck %s
+; RUN: not llc -o /dev/null %s -mtriple=i386-unknown-unknown -mattr=avx512vl 2>&1 | FileCheck %s
 
 ; CHECK: error: couldn't allocate output register for constraint '{xmm16}'
 define i64 @blup() {