[PATCH] D43374: [ARM]Decoding MSR with unpredictable destination register causes an assert

[Simi Pallipurath via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
simpal01 marked an inline comment as done.
Closed by commit rL326803: [ARM]Decoding MSR with unpredictable destination register causes an assert (authored by simpal01, committed by ).

Changed prior to commit:
  https://reviews.llvm.org/D43374?vs=136700&id=137192#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D43374

Files:
  llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
  llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
  llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
  llvm/trunk/test/MC/ARM/thumbv8m.s
  llvm/trunk/test/MC/Disassembler/ARM/invalid-thumb-MSR-MClass.txt

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D43374.137192.patch
Type: text/x-patch
Size: 3896 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20180306/e3355d01/attachment.bin>