[llvm] r326803 - [ARM]Decoding MSR with unpredictable destination register causes an assert
Simi Pallipurath via llvm-commits
llvm-commits at lists.llvm.org
Tue Mar 6 07:21:19 PST 2018
Author: simpal01
Date: Tue Mar 6 07:21:19 2018
New Revision: 326803
URL: http://llvm.org/viewvc/llvm-project?rev=326803&view=rev
Log:
[ARM]Decoding MSR with unpredictable destination register causes an assert
This patch handling:
Enable parsing of raw encodings of system registers .
Allows UNPREDICTABLE sysregs to be decoded to a raw number in the same way that disasslib does, rather than llvm crashing.
Disassemble msr/mrs with unpredictable sysregs as SoftFail.
Fix regression due to SoftFailing some encodings.
Patch by Chris Ryder
Differential revision:https://reviews.llvm.org/D43374
Modified:
llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
llvm/trunk/test/MC/ARM/thumbv8m.s
llvm/trunk/test/MC/Disassembler/ARM/invalid-thumb-MSR-MClass.txt
Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=326803&r1=326802&r2=326803&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Tue Mar 6 07:21:19 2018
@@ -4238,6 +4238,18 @@ ARMAsmParser::parseMSRMaskOperand(Operan
MCAsmParser &Parser = getParser();
SMLoc S = Parser.getTok().getLoc();
const AsmToken &Tok = Parser.getTok();
+
+ if (Tok.is(AsmToken::Integer)) {
+ int64_t Val = Tok.getIntVal();
+ if (Val > 255 || Val < 0) {
+ return MatchOperand_NoMatch;
+ }
+ unsigned SYSmvalue = Val & 0xFF;
+ Parser.Lex();
+ Operands.push_back(ARMOperand::CreateMSRMask(SYSmvalue, S));
+ return MatchOperand_Success;
+ }
+
if (!Tok.is(AsmToken::Identifier))
return MatchOperand_NoMatch;
StringRef Mask = Tok.getString();
Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp?rev=326803&r1=326802&r2=326803&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp Tue Mar 6 07:21:19 2018
@@ -4149,7 +4149,6 @@ static DecodeStatus DecodeMSRMask(MCInst
case 0x8a: // msplim_ns
case 0x8b: // psplim_ns
case 0x91: // basepri_ns
- case 0x92: // basepri_max_ns
case 0x93: // faultmask_ns
if (!(FeatureBits[ARM::HasV8MMainlineOps]))
return MCDisassembler::Fail;
@@ -4165,7 +4164,9 @@ static DecodeStatus DecodeMSRMask(MCInst
return MCDisassembler::Fail;
break;
default:
- return MCDisassembler::Fail;
+ // Architecturally defined as unpredictable
+ S = MCDisassembler::SoftFail;
+ break;
}
if (Inst.getOpcode() == ARM::t2MSR_M) {
Modified: llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp?rev=326803&r1=326802&r2=326803&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp Tue Mar 6 07:21:19 2018
@@ -825,7 +825,8 @@ void ARMInstPrinter::printMSRMaskOperand
return;
}
- llvm_unreachable("Unexpected mask value!");
+ O << SYSm;
+
return;
}
Modified: llvm/trunk/test/MC/ARM/thumbv8m.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/thumbv8m.s?rev=326803&r1=326802&r2=326803&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/thumbv8m.s (original)
+++ llvm/trunk/test/MC/ARM/thumbv8m.s Tue Mar 6 07:21:19 2018
@@ -225,6 +225,12 @@ MSR FAULTMASK_NS, r14
// CHECK-MAINLINE: msr faultmask_ns, lr @ encoding: [0x8e,0xf3,0x93,0x88]
// UNDEF-BASELINE: error: invalid operand for instruction
+// Unpredictable SYSm's
+MRS r8, 146
+// CHECK: mrs r8, 146 @ encoding: [0xef,0xf3,0x92,0x88]
+MSR 146, r8
+// CHECK: msr 146, r8 @ encoding: [0x88,0xf3,0x92,0x80]
+
// Invalid operand tests
// UNDEF: error: too many operands for instruction
// UNDEF: sg #0
Modified: llvm/trunk/test/MC/Disassembler/ARM/invalid-thumb-MSR-MClass.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/invalid-thumb-MSR-MClass.txt?rev=326803&r1=326802&r2=326803&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/invalid-thumb-MSR-MClass.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/invalid-thumb-MSR-MClass.txt Tue Mar 6 07:21:19 2018
@@ -1,12 +1,12 @@
-# RUN: not llvm-mc -disassemble %s -triple=thumbv7em 2>&1 | FileCheck %s
-# RUN: not llvm-mc -disassemble %s -triple=thumbv7m 2>&1 | FileCheck --check-prefix=CHECK --check-prefix=CHECK-V7M %s
+# RUN: llvm-mc -disassemble %s -triple=thumbv7em 2>&1 | FileCheck %s
+# RUN: llvm-mc -disassemble %s -triple=thumbv7m 2>&1 | FileCheck --check-prefix=CHECK --check-prefix=CHECK-V7M %s
#------------------------------------------------------------------------------
# Undefined encodings for mrs
#------------------------------------------------------------------------------
# invalid SYSm
-# CHECK: warning: invalid instruction encoding
+# CHECK: warning: potentially undefined instruction encoding
# CHECK-NEXT: [0xef 0xf3 0x80 0x80]
[0xef 0xf3 0x80 0x80]
@@ -30,6 +30,6 @@
[0x80 0xf3 0x00 0x84]
# invalid SYSm
-# CHECK: warning: invalid instruction encoding
+# CHECK: warning: potentially undefined instruction encoding
# CHECK-NEXT: [0x80 0xf3 0x80 0x88]
[0x80 0xf3 0x80 0x88]
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