[llvm] r326470 - AMDGPU/GlobalISel: Define instruction mapping for G_IMPLICIT_DEF
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Thu Mar 1 11:16:52 PST 2018
Author: arsenm
Date: Thu Mar 1 11:16:52 2018
New Revision: 326470
URL: http://llvm.org/viewvc/llvm-project?rev=326470&view=rev
Log:
AMDGPU/GlobalISel: Define instruction mapping for G_IMPLICIT_DEF
Patch by Tom Stellard
Modified:
llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-default.mir
Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp?rev=326470&r1=326469&r2=326470&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp Thu Mar 1 11:16:52 2018
@@ -54,6 +54,9 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo
setAction({G_FCONSTANT, S32}, Legal);
setAction({G_FCONSTANT, S64}, Legal);
+ setAction({G_IMPLICIT_DEF, S32}, Legal);
+ setAction({G_IMPLICIT_DEF, S64}, Legal);
+
setAction({G_FADD, S32}, Legal);
setAction({G_FCMP, S1}, Legal);
Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp?rev=326470&r1=326469&r2=326470&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp Thu Mar 1 11:16:52 2018
@@ -174,6 +174,11 @@ AMDGPURegisterBankInfo::getInstrMapping(
default:
IsComplete = false;
break;
+ case AMDGPU::G_IMPLICIT_DEF: {
+ unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
+ OpdsMapping[0] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size);
+ break;
+ }
case AMDGPU::G_FCONSTANT:
case AMDGPU::G_CONSTANT: {
unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
Modified: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-default.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-default.mir?rev=326470&r1=326469&r2=326470&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-default.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-default.mir Thu Mar 1 11:16:52 2018
@@ -1,31 +1,52 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -march amdgcn -mcpu=fiji -run-pass=regbankselect -global-isel %s -o - | FileCheck %s
# Check the default mappings for various instructions.
---
-# CHECK-LABEL: name: test_fconstant_f32_1
name: test_fconstant_f32_1
legalized: true
body: |
bb.0:
- ; CHECK: %0:sgpr(s32) = G_FCONSTANT float 1.0
+ ; CHECK-LABEL: name: test_fconstant_f32_1
+ ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 1.000000e+00
%0:_(s32) = G_FCONSTANT float 1.0
...
---
-# CHECK-LABEL: name: test_fconstant_f64_1
name: test_fconstant_f64_1
legalized: true
body: |
bb.0:
- ; CHECK: %0:sgpr(s64) = G_FCONSTANT double 1.0
+ ; CHECK-LABEL: name: test_fconstant_f64_1
+ ; CHECK: [[C:%[0-9]+]]:sgpr(s64) = G_FCONSTANT double 1.000000e+00
%0:_(s64) = G_FCONSTANT double 1.0
...
---
-# CHECK-LABEL: name: test_fconstant_f16_1
name: test_fconstant_f16_1
legalized: true
body: |
bb.0:
- ; CHECK: %0:sgpr(s32) = G_FCONSTANT half 0xH3C00
+ ; CHECK-LABEL: name: test_fconstant_f16_1
+ ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_FCONSTANT half 0xH3C00
%0:_(s32) = G_FCONSTANT half 1.0
...
+
+---
+name: test_implicit_def_s32
+legalized: true
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: test_implicit_def_s32
+ ; CHECK: [[DEF:%[0-9]+]]:sgpr(s32) = G_IMPLICIT_DEF
+ %0:_(s32) = G_IMPLICIT_DEF
+...
+
+---
+name: test_implicit_def_s64
+legalized: true
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: test_implicit_def_s64
+ ; CHECK: [[DEF:%[0-9]+]]:sgpr(s64) = G_IMPLICIT_DEF
+ %0:_(s64) = G_IMPLICIT_DEF
+...
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