[PATCH] D41932: [RISCV] Hooks for enabling instruction compression

[Ana Pazos via Phabricator via llvm-commits]

apazos planned changes to this revision.
apazos added a comment.

We need to put in the debugger to double check the flow, I recall this flow:
 .s ->.o
AsmParser.cpp ->...-> RISCVAsmParser::MatchAndEmitInstruction-> MatchInstructionImpl-> Out.EmitInstruction…
.o->.s
Disassemble.cpp -> ... ->Streamer.EmitInstruction(Inst, STI);-> InstPrinter->printInst(&Inst, OS, "", STI);-> printInstruction(MI, STI, O) in RISCVInstrPrinter

The goal was to try to compress the instr before emitting the instr. And uncompress the instr when printing, depending on the alias flag.


https://reviews.llvm.org/D41932