[PATCH] D41932: [RISCV] Hooks for enabling instruction compression

[Alex Bradbury via Phabricator via llvm-commits]

asb added inline comments.


================
Comment at: lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp:53
+  bool Res = compressInst(CInst, Inst, STI, getContext());
+  MCELFStreamer::EmitInstruction((Res ? CInst : Inst), STI);
+}
----------------
asb wrote:
> apazos wrote:
> > The instruction will only be transformed if compression extension is enabled.
> > If the user enables compression, but does not want a particular instruction to be compressed, RISCV has no assembler directive to allow that (does it Alex? Maybe we can request that feature?). As Eli knows ARM supports "adds.w" to allow that kind of  fine grain control.
> > We need to also check if LowerRISCVMachineInstrToMCInst is invoked when coming from assembly/disassembly path.
> There is no current directive to control automatic compression separately from support for the C extension. If you want to compile an assembly file with support for the C extension but have complete control over when compressed instructions are chosen you currently need to use .option rvc and .option norvc (in gas - not yet implemented in llvm-mc). e.g.
> 
> 
> ```
> .option norvc
> addi x1, x1, 1
> .option rvc
> c.addi x1, 1
> ```
I do think it would be good to have an option for this. I identified this lack in <https://github.com/riscv/riscv-toolchain-conventions#issues-for-consideration-4>, and it would probably be worth trying again to engage the GCC devs and RISC-V community in trying to address some of the holes detailed in my toolchain-conventions document.


https://reviews.llvm.org/D41932