[PATCH] D43641: [PowerPC] Code cleanup. Remove instructions that were withdrawn from Power 9.

Stefan Pintilie via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Thu Feb 22 12:19:21 PST 2018


stefanp created this revision.
stefanp added reviewers: kbarton, nemanjai, inouehrs, sfertile, lei, syzaara, echristo, hfinkel.

The following set of instructions was originally planned to be added for Power 9 and so code was added to support them. However, a decision was made later on to withdraw support for these instructions in the hardware.  
xscmpnedp
xvcmpnesp
xvcmpnedp
This patch removes support for the instructions that were not added.


https://reviews.llvm.org/D43641

Files:
  lib/Target/PowerPC/PPCInstrVSX.td
  test/MC/Disassembler/PowerPC/vsx.txt
  test/MC/PowerPC/vsx.s


Index: test/MC/PowerPC/vsx.s
===================================================================
--- test/MC/PowerPC/vsx.s
+++ test/MC/PowerPC/vsx.s
@@ -643,7 +643,7 @@
 # CHECK-LE: xscmpexpqp 6, 31, 27               # encoding: [0x48,0xd9,0x1f,0xff]
             xscmpexpqp 6, 31, 27
 
-# Compare ==, >=, >, !=
+# Compare ==, >=, >
 # CHECK-BE: xscmpeqdp 7, 63, 27                # encoding: [0xf0,0xff,0xd8,0x1c]
 # CHECK-LE: xscmpeqdp 7, 63, 27                # encoding: [0x1c,0xd8,0xff,0xf0]
             xscmpeqdp 7, 63, 27
@@ -653,23 +653,6 @@
 # CHECK-BE: xscmpgtdp 7, 63, 27                # encoding: [0xf0,0xff,0xd8,0x5c]
 # CHECK-LE: xscmpgtdp 7, 63, 27                # encoding: [0x5c,0xd8,0xff,0xf0]
             xscmpgtdp 7, 63, 27
-# CHECK-BE: xscmpnedp 7, 63, 27                # encoding: [0xf0,0xff,0xd8,0xdc]
-# CHECK-LE: xscmpnedp 7, 63, 27                # encoding: [0xdc,0xd8,0xff,0xf0]
-            xscmpnedp 7, 63, 27
-
-# Vector Compare Not Equal
-# CHECK-BE: xvcmpnedp 7, 63, 27                # encoding: [0xf0,0xff,0xdb,0xdc]
-# CHECK-LE: xvcmpnedp 7, 63, 27                # encoding: [0xdc,0xdb,0xff,0xf0]
-            xvcmpnedp 7, 63, 27
-# CHECK-BE: xvcmpnedp. 7, 63, 27               # encoding: [0xf0,0xff,0xdf,0xdc]
-# CHECK-LE: xvcmpnedp. 7, 63, 27               # encoding: [0xdc,0xdf,0xff,0xf0]
-            xvcmpnedp. 7, 63, 27
-# CHECK-BE: xvcmpnesp 7, 63, 27                # encoding: [0xf0,0xff,0xda,0xdc]
-# CHECK-LE: xvcmpnesp 7, 63, 27                # encoding: [0xdc,0xda,0xff,0xf0]
-            xvcmpnesp 7, 63, 27
-# CHECK-BE: xvcmpnesp. 7, 63, 27               # encoding: [0xf0,0xff,0xde,0xdc]
-# CHECK-LE: xvcmpnesp. 7, 63, 27               # encoding: [0xdc,0xde,0xff,0xf0]
-            xvcmpnesp. 7, 63, 27
 
 # Convert DP -> QP
 # CHECK-BE: xscvdpqp 7, 27                     # encoding: [0xfc,0xf6,0xde,0x88]
Index: test/MC/Disassembler/PowerPC/vsx.txt
===================================================================
--- test/MC/Disassembler/PowerPC/vsx.txt
+++ test/MC/Disassembler/PowerPC/vsx.txt
@@ -629,21 +629,6 @@
 # CHECK: xscmpgtdp 7, 63, 27
 0xf0 0xff 0xd8 0x5c
 
-# CHECK: xscmpnedp 7, 63, 27
-0xf0 0xff 0xd8 0xdc
-
-# CHECK: xvcmpnedp 7, 63, 27
-0xf0 0xff 0xdb 0xdc
-
-# CHECK: xvcmpnedp. 7, 63, 27
-0xf0 0xff 0xdf 0xdc
-
-# CHECK: xvcmpnesp 7, 63, 27
-0xf0 0xff 0xda 0xdc
-
-# CHECK: xvcmpnesp. 7, 63, 27
-0xf0 0xff 0xde 0xdc
-
 # CHECK: xscvdpqp 7, 27
 0xfc 0xf6 0xde 0x88
 
Index: lib/Target/PowerPC/PPCInstrVSX.td
===================================================================
--- lib/Target/PowerPC/PPCInstrVSX.td
+++ lib/Target/PowerPC/PPCInstrVSX.td
@@ -2434,27 +2434,6 @@
                                   IIC_FPCompare, []>;
   def XSCMPGTDP : XX3_XT5_XA5_XB5<60, 11, "xscmpgtdp", vsrc, vsfrc, vsfrc,
                                   IIC_FPCompare, []>;
-  def XSCMPNEDP : XX3_XT5_XA5_XB5<60, 27, "xscmpnedp", vsrc, vsfrc, vsfrc,
-                                  IIC_FPCompare, []>;
-  let UseVSXReg = 1 in {
-  // Vector Compare Not Equal
-  def XVCMPNEDP  : XX3Form_Rc<60, 123,
-                              (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
-                              "xvcmpnedp  $XT, $XA, $XB", IIC_VecFPCompare, []>;
-  let Defs = [CR6] in
-  def XVCMPNEDPo : XX3Form_Rc<60, 123,
-                              (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
-                              "xvcmpnedp. $XT, $XA, $XB", IIC_VecFPCompare, []>,
-                              isDOT;
-  def XVCMPNESP  : XX3Form_Rc<60,  91,
-                              (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
-                              "xvcmpnesp  $XT, $XA, $XB", IIC_VecFPCompare, []>;
-  let Defs = [CR6] in
-  def XVCMPNESPo : XX3Form_Rc<60,  91,
-                              (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
-                              "xvcmpnesp. $XT, $XA, $XB", IIC_VecFPCompare, []>,
-                              isDOT;
-  } // UseVSXReg = 1
 
   //===--------------------------------------------------------------------===//
   // Quad-Precision Floating-Point Conversion Instructions:


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