[PATCH] D43380: [X86] Disable CLWB in Cannon Lake

[Gabor Buella via Phabricator via llvm-commits]

GBuella added a comment.

In https://reviews.llvm.org/D43380#1010942, @craig.topper wrote:

> I thought our assemble stance was that everything was available all the time. For example, the bug a few weeks back that said we should always parse xmm16-xmm31 registers regardless of avx512 enabling. Or are we saying we should support everything unlesss you pick a specific CPU?


Yes, the MC assembler allows any instruction, so this patch has no relation to that.


Repository:
  rL LLVM

https://reviews.llvm.org/D43380