[PATCH] D43380: [X86] Disable CLWB in Cannon Lake
Gabor Buella via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Feb 20 01:47:05 PST 2018
GBuella updated this revision to Diff 135022.
GBuella added a comment.
Adding tests for checking that the
cpu flags affect clwb intrinsic usage as they
should.
Repository:
rL LLVM
https://reviews.llvm.org/D43380
Files:
lib/Target/X86/X86.td
test/CodeGen/X86/clwb.ll
Index: test/CodeGen/X86/clwb.ll
===================================================================
--- test/CodeGen/X86/clwb.ll
+++ test/CodeGen/X86/clwb.ll
@@ -1,5 +1,12 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; NOTE: clwb is available in Skylake Server, not available in the newer
+; NOTE: Cannon Lake arch, but available again in the newer Ice Lake arch.
; RUN: llc < %s -mtriple=i686-apple-darwin -mattr=clwb | FileCheck %s
+; RUN: llc < %s -mtriple=i686-apple-darwin -mcpu=skx | FileCheck %s
+; RUN: not llc < %s -mtriple=i686-apple-darwin -mcpu=cannonlake 2>&1 | FileCheck %s --check-prefix=CNL
+; RUN: llc < %s -mtriple=i686-apple-darwin -mcpu=icelake | FileCheck %s
+
+; CNL: LLVM ERROR: Cannot select: intrinsic %llvm.x86.clwb
define void @clwb(i8* %p) nounwind {
; CHECK-LABEL: clwb:
Index: lib/Target/X86/X86.td
===================================================================
--- lib/Target/X86/X86.td
+++ lib/Target/X86/X86.td
@@ -781,7 +781,13 @@
def : SkylakeServerProc<"skylake-avx512">;
def : SkylakeServerProc<"skx">; // Legacy alias.
-def CNLFeatures : ProcessorFeatures<SKXFeatures.Value, [
+def CNLFeatures : ProcessorFeatures<SKLFeatures.Value, [
+ FeatureAVX512,
+ FeatureCDI,
+ FeatureDQI,
+ FeatureBWI,
+ FeatureVLX,
+ FeaturePKU,
FeatureVBMI,
FeatureIFMA,
FeatureSHA
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