[PATCH] D43274: [RegisterClassInfo] Invalidate the register pressure set limit cache when reserved regs or callee saved regs change

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This revision was automatically updated to reflect the committed changes.
Closed by commit rL325153: [RegisterClassInfo] Invalidate the register pressure set limit cache when… (authored by ctopper, committed by ).

Changed prior to commit:
  https://reviews.llvm.org/D43274?vs=134157&id=134268#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D43274

Files:
  llvm/trunk/lib/CodeGen/RegisterClassInfo.cpp


Index: llvm/trunk/lib/CodeGen/RegisterClassInfo.cpp
===================================================================
--- llvm/trunk/lib/CodeGen/RegisterClassInfo.cpp
+++ llvm/trunk/lib/CodeGen/RegisterClassInfo.cpp
@@ -49,9 +49,6 @@
   if (MF->getSubtarget().getRegisterInfo() != TRI) {
     TRI = MF->getSubtarget().getRegisterInfo();
     RegClass.reset(new RCInfo[TRI->getNumRegClasses()]);
-    unsigned NumPSets = TRI->getNumRegPressureSets();
-    PSetLimits.reset(new unsigned[NumPSets]);
-    std::fill(&PSetLimits[0], &PSetLimits[NumPSets], 0);
     Update = true;
   }
 
@@ -80,8 +77,12 @@
   }
 
   // Invalidate cached information from previous function.
-  if (Update)
+  if (Update) {
+    unsigned NumPSets = TRI->getNumRegPressureSets();
+    PSetLimits.reset(new unsigned[NumPSets]);
+    std::fill(&PSetLimits[0], &PSetLimits[NumPSets], 0);
     ++Tag;
+  }
 }
 
 /// compute - Compute the preferred allocation order for RC with reserved


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