[llvm] r324746 - AMDGPU: Fix layering issue

[Hans Wennborg via llvm-commits]

Merged to 6.0 in r325007.

On Fri, Feb 9, 2018 at 5:57 PM, Matt Arsenault via llvm-commits
<llvm-commits at lists.llvm.org> wrote:
> Author: arsenm
> Date: Fri Feb  9 08:57:48 2018
> New Revision: 324746
>
> URL: http://llvm.org/viewvc/llvm-project?rev=324746&view=rev
> Log:
> AMDGPU: Fix layering issue
>
> Move utility function that depends on codegen.
> Fixes build with r324487 reapplied.
>
> Modified:
>     llvm/trunk/lib/Target/AMDGPU/AMDGPUInstrInfo.cpp
>     llvm/trunk/lib/Target/AMDGPU/AMDGPUInstrInfo.h
>     llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
>     llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp
>     llvm/trunk/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
>     llvm/trunk/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
>
> Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPUInstrInfo.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUInstrInfo.cpp?rev=324746&r1=324745&r2=324746&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/AMDGPU/AMDGPUInstrInfo.cpp (original)
> +++ llvm/trunk/lib/Target/AMDGPU/AMDGPUInstrInfo.cpp Fri Feb  9 08:57:48 2018
> @@ -115,3 +115,21 @@ int AMDGPUInstrInfo::pseudoToMCOpcode(in
>
>    return MCOp;
>  }
> +
> +// TODO: Should largely merge with AMDGPUTTIImpl::isSourceOfDivergence.
> +bool AMDGPUInstrInfo::isUniformMMO(const MachineMemOperand *MMO) {
> +  const Value *Ptr = MMO->getValue();
> +  // UndefValue means this is a load of a kernel input.  These are uniform.
> +  // Sometimes LDS instructions have constant pointers.
> +  // If Ptr is null, then that means this mem operand contains a
> +  // PseudoSourceValue like GOT.
> +  if (!Ptr || isa<UndefValue>(Ptr) ||
> +      isa<Constant>(Ptr) || isa<GlobalValue>(Ptr))
> +    return true;
> +
> +  if (const Argument *Arg = dyn_cast<Argument>(Ptr))
> +    return AMDGPU::isArgPassedInSGPR(Arg);
> +
> +  const Instruction *I = dyn_cast<Instruction>(Ptr);
> +  return I && I->getMetadata("amdgpu.uniform");
> +}
>
> Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPUInstrInfo.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUInstrInfo.h?rev=324746&r1=324745&r2=324746&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/AMDGPU/AMDGPUInstrInfo.h (original)
> +++ llvm/trunk/lib/Target/AMDGPU/AMDGPUInstrInfo.h Fri Feb  9 08:57:48 2018
> @@ -50,6 +50,8 @@ public:
>    /// Return -1 if the target-specific opcode for the pseudo instruction does
>    /// not exist. If Opcode is not a pseudo instruction, this is identity.
>    int pseudoToMCOpcode(int Opcode) const;
> +
> +  static bool isUniformMMO(const MachineMemOperand *MMO);
>  };
>  } // End llvm namespace
>
>
> Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp?rev=324746&r1=324745&r2=324746&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp (original)
> +++ llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp Fri Feb  9 08:57:48 2018
> @@ -120,7 +120,7 @@ static bool isInstrUniform(const Machine
>      return false;
>
>    const MachineMemOperand *MMO = *MI.memoperands_begin();
> -  return AMDGPU::isUniformMMO(MMO);
> +  return AMDGPUInstrInfo::isUniformMMO(MMO);
>  }
>
>  const RegisterBankInfo::InstructionMapping &
>
> Modified: llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp?rev=324746&r1=324745&r2=324746&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp Fri Feb  9 08:57:48 2018
> @@ -1095,7 +1095,7 @@ bool SITargetLowering::isCheapAddrSpaceC
>  bool SITargetLowering::isMemOpUniform(const SDNode *N) const {
>    const MemSDNode *MemNode = cast<MemSDNode>(N);
>
> -  return AMDGPU::isUniformMMO(MemNode->getMemOperand());
> +  return AMDGPUInstrInfo::isUniformMMO(MemNode->getMemOperand());
>  }
>
>  TargetLoweringBase::LegalizeTypeAction
>
> Modified: llvm/trunk/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp?rev=324746&r1=324745&r2=324746&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp (original)
> +++ llvm/trunk/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp Fri Feb  9 08:57:48 2018
> @@ -905,24 +905,6 @@ bool isArgPassedInSGPR(const Argument *A
>    }
>  }
>
> -// TODO: Should largely merge with AMDGPUTTIImpl::isSourceOfDivergence.
> -bool isUniformMMO(const MachineMemOperand *MMO) {
> -  const Value *Ptr = MMO->getValue();
> -  // UndefValue means this is a load of a kernel input.  These are uniform.
> -  // Sometimes LDS instructions have constant pointers.
> -  // If Ptr is null, then that means this mem operand contains a
> -  // PseudoSourceValue like GOT.
> -  if (!Ptr || isa<UndefValue>(Ptr) ||
> -      isa<Constant>(Ptr) || isa<GlobalValue>(Ptr))
> -    return true;
> -
> -  if (const Argument *Arg = dyn_cast<Argument>(Ptr))
> -    return isArgPassedInSGPR(Arg);
> -
> -  const Instruction *I = dyn_cast<Instruction>(Ptr);
> -  return I && I->getMetadata("amdgpu.uniform");
> -}
> -
>  int64_t getSMRDEncodedOffset(const MCSubtargetInfo &ST, int64_t ByteOffset) {
>    if (isGCN3Encoding(ST))
>      return ByteOffset;
>
> Modified: llvm/trunk/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h?rev=324746&r1=324745&r2=324746&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h (original)
> +++ llvm/trunk/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h Fri Feb  9 08:57:48 2018
> @@ -372,7 +372,6 @@ LLVM_READNONE
>  bool isInlinableLiteralV216(int32_t Literal, bool HasInv2Pi);
>
>  bool isArgPassedInSGPR(const Argument *Arg);
> -bool isUniformMMO(const MachineMemOperand *MMO);
>
>  /// \returns The encoding that will be used for \p ByteOffset in the SMRD
>  /// offset field.
>
>
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