[PATCH] D43090: GlobalISel: IRTranslate llvm.fmuladd.* intrinsic
Volkan Keles via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Feb 12 16:49:57 PST 2018
This revision was automatically updated to reflect the committed changes.
Closed by commit rL324971: GlobalISel: IRTranslate llvm.fmuladd.* intrinsic (authored by volkan, committed by ).
Changed prior to commit:
https://reviews.llvm.org/D43090?vs=133962&id=133963#toc
Repository:
rL LLVM
https://reviews.llvm.org/D43090
Files:
llvm/trunk/lib/CodeGen/GlobalISel/IRTranslator.cpp
llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-fmuladd.ll
Index: llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-fmuladd.ll
===================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-fmuladd.ll
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-fmuladd.ll
@@ -0,0 +1,34 @@
+; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+; RUN: llc -o - -verify-machineinstrs -global-isel -stop-after=irtranslator -fp-contract=fast %s | FileCheck %s --check-prefix=FPFAST
+; RUN: llc -o - -verify-machineinstrs -global-isel -stop-after=irtranslator -fp-contract=off %s | FileCheck %s --check-prefix=FPOFF
+target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
+target triple = "aarch64--"
+
+define float @test_fmuladd(float %x, float %y, float %z) {
+ ; FPFAST-LABEL: name: test_fmuladd
+ ; FPFAST: bb.1 (%ir-block.0):
+ ; FPFAST: liveins: $s0, $s1, $s2
+ ; FPFAST: [[COPY:%[0-9]+]]:_(s32) = COPY $s0
+ ; FPFAST: [[COPY1:%[0-9]+]]:_(s32) = COPY $s1
+ ; FPFAST: [[COPY2:%[0-9]+]]:_(s32) = COPY $s2
+ ; FPFAST: [[FMA:%[0-9]+]]:_(s32) = G_FMA [[COPY]], [[COPY1]], [[COPY2]]
+ ; FPFAST: $s0 = COPY [[FMA]](s32)
+ ; FPFAST: RET_ReallyLR implicit $s0
+ ; FPOFF-LABEL: name: test_fmuladd
+ ; FPOFF: bb.1 (%ir-block.0):
+ ; FPOFF: liveins: $s0, $s1, $s2
+ ; FPOFF: [[COPY:%[0-9]+]]:_(s32) = COPY $s0
+ ; FPOFF: [[COPY1:%[0-9]+]]:_(s32) = COPY $s1
+ ; FPOFF: [[COPY2:%[0-9]+]]:_(s32) = COPY $s2
+ ; FPOFF: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[COPY]], [[COPY1]]
+ ; FPOFF: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FMUL]], [[COPY2]]
+ ; FPOFF: $s0 = COPY [[FADD]](s32)
+ ; FPOFF: RET_ReallyLR implicit $s0
+ %res = call float @llvm.fmuladd.f32(float %x, float %y, float %z)
+ ret float %res
+}
+
+; Function Attrs: nounwind readnone speculatable
+declare float @llvm.fmuladd.f32(float, float, float) #0
+
+attributes #0 = { nounwind readnone speculatable }
Index: llvm/trunk/lib/CodeGen/GlobalISel/IRTranslator.cpp
===================================================================
--- llvm/trunk/lib/CodeGen/GlobalISel/IRTranslator.cpp
+++ llvm/trunk/lib/CodeGen/GlobalISel/IRTranslator.cpp
@@ -753,6 +753,25 @@
.addUse(getOrCreateVReg(*CI.getArgOperand(1)))
.addUse(getOrCreateVReg(*CI.getArgOperand(2)));
return true;
+ case Intrinsic::fmuladd: {
+ const TargetMachine &TM = MF->getTarget();
+ const TargetLowering &TLI = *MF->getSubtarget().getTargetLowering();
+ unsigned Dst = getOrCreateVReg(CI);
+ unsigned Op0 = getOrCreateVReg(*CI.getArgOperand(0));
+ unsigned Op1 = getOrCreateVReg(*CI.getArgOperand(1));
+ unsigned Op2 = getOrCreateVReg(*CI.getArgOperand(2));
+ if (TM.Options.AllowFPOpFusion != FPOpFusion::Strict &&
+ TLI.isFMAFasterThanFMulAndFAdd(TLI.getValueType(*DL, CI.getType()))) {
+ // TODO: Revisit this to see if we should move this part of the
+ // lowering to the combiner.
+ MIRBuilder.buildInstr(TargetOpcode::G_FMA, Dst, Op0, Op1, Op2);
+ } else {
+ LLT Ty = getLLTForType(*CI.getType(), *DL);
+ auto FMul = MIRBuilder.buildInstr(TargetOpcode::G_FMUL, Ty, Op0, Op1);
+ MIRBuilder.buildInstr(TargetOpcode::G_FADD, Dst, FMul, Op2);
+ }
+ return true;
+ }
case Intrinsic::memcpy:
case Intrinsic::memmove:
case Intrinsic::memset:
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