[PATCH] D43014: [X86][SSE] Enable SMIN/SMAX/UMIN/UMAX custom lowering for all legal types

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added inline comments.


================
Comment at: lib/Target/X86/X86ISelLowering.cpp:22023
+  // using the SMIN/SMAX instructions and flipping the signbit back.
+  if (VT == MVT::v8i16) {
+    assert((Opcode == ISD::UMIN || Opcode == ISD::UMAX) &&
----------------
craig.topper wrote:
> RKSimon wrote:
> > craig.topper wrote:
> > > What if we can prove the sign bit is 0? Or do we already do that in some DAG combine?
> > We currently don't (we don't do much to combine integer MINMAX functions at all), but it's an easy fix in DAGCombine.
> Does this trick also work in reverse for MVT::v16i8?
Technically yes - but the current codegen of PCMPGTB/AND/ANDN/OR gives the same number of instructions and avoids the signmask constant. The main use of this sign flip trick is that it removes the unsigned integer compare.


Repository:
  rL LLVM

https://reviews.llvm.org/D43014