[PATCH] D43014: [X86][SSE] Enable SMIN/SMAX/UMIN/UMAX custom lowering for all legal types

[Craig Topper via Phabricator via llvm-commits]

craig.topper accepted this revision.
craig.topper added a comment.
This revision is now accepted and ready to land.

LGTM other than that question about MVT::v16i8



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Comment at: lib/Target/X86/X86ISelLowering.cpp:22023
+  // using the SMIN/SMAX instructions and flipping the signbit back.
+  if (VT == MVT::v8i16) {
+    assert((Opcode == ISD::UMIN || Opcode == ISD::UMAX) &&
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RKSimon wrote:
> craig.topper wrote:
> > What if we can prove the sign bit is 0? Or do we already do that in some DAG combine?
> We currently don't (we don't do much to combine integer MINMAX functions at all), but it's an easy fix in DAGCombine.
Does this trick also work in reverse for MVT::v16i8?


Repository:
  rL LLVM

https://reviews.llvm.org/D43014