[PATCH] D42981: [COST] Fix cost model of load instructions on X86

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added inline comments.


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Comment at: lib/Target/X86/X86TargetTransformInfo.cpp:1824
+           !isa<LoadInst>(I->getOperand(1)) || I->getOperand(0) == OpI;
+  case Instruction::Mul:
+    return (!isa<LoadInst>(I->getOperand(0)) ||
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A little tricky, but we only fold certain operands (Operand(1) typically) so if it doesn't commute then we can't fold - ISD::SUB/FSUB/FDIV/SHL/ASHR/LSHR will all definitely be affected by this.

Also we need to handle the case where both operands are loads - we will still have at least one load cost.


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Comment at: test/Transforms/SLPVectorizer/X86/arith-mul.ll:265
+; SLM-NEXT:    store i32 [[R14]], i32* getelementptr inbounds ([16 x i32], [16 x i32]* @c32, i32 0, i64 14), align 4
+; SLM-NEXT:    store i32 [[R15]], i32* getelementptr inbounds ([16 x i32], [16 x i32]* @c32, i32 0, i64 15), align 4
 ; SLM-NEXT:    ret void
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This looks like a cost model issue - scalar integer muls on silvermont are pretty awful just like the vector imuls.....


Repository:
  rL LLVM

https://reviews.llvm.org/D42981