[llvm] r324063 - [SelectionDAG] Consider endianness in scalarizeVectorStore().
Jonas Paulsson via llvm-commits
llvm-commits at lists.llvm.org
Fri Feb 2 00:48:02 PST 2018
Author: jonpa
Date: Fri Feb 2 00:48:02 2018
New Revision: 324063
URL: http://llvm.org/viewvc/llvm-project?rev=324063&view=rev
Log:
[SelectionDAG] Consider endianness in scalarizeVectorStore().
When handling vectors with non byte-sized elements, reverse the order of the
elements in the built integer if the target is Big-Endian.
SystemZ tests updated.
Review: Eli Friedman, Ulrich Weigand.
https://reviews.llvm.org/D42786
Modified:
llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp
llvm/trunk/test/CodeGen/SystemZ/store_nonbytesized_vecs.ll
llvm/trunk/test/CodeGen/SystemZ/vec-move-17.ll
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp?rev=324063&r1=324062&r2=324063&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Fri Feb 2 00:48:02 2018
@@ -3457,9 +3457,12 @@ SDValue TargetLowering::scalarizeVectorS
DAG.getConstant(Idx, SL, IdxVT));
SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SL, MemSclVT, Elt);
SDValue ExtElt = DAG.getNode(ISD::ZERO_EXTEND, SL, IntVT, Trunc);
+ unsigned ShiftIntoIdx =
+ (DAG.getDataLayout().isBigEndian() ? (NumElem - 1) - Idx : Idx);
SDValue ShiftAmount =
- DAG.getConstant(Idx * MemSclVT.getSizeInBits(), SL, IntVT);
- SDValue ShiftedElt = DAG.getNode(ISD::SHL, SL, IntVT, ExtElt, ShiftAmount);
+ DAG.getConstant(ShiftIntoIdx * MemSclVT.getSizeInBits(), SL, IntVT);
+ SDValue ShiftedElt =
+ DAG.getNode(ISD::SHL, SL, IntVT, ExtElt, ShiftAmount);
CurrVal = DAG.getNode(ISD::OR, SL, IntVT, CurrVal, ShiftedElt);
}
Modified: llvm/trunk/test/CodeGen/SystemZ/store_nonbytesized_vecs.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/store_nonbytesized_vecs.ll?rev=324063&r1=324062&r2=324063&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/store_nonbytesized_vecs.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/store_nonbytesized_vecs.ll Fri Feb 2 00:48:02 2018
@@ -5,18 +5,18 @@
define void @fun0(<4 x i31> %src, <4 x i31>* %p)
; CHECK-LABEL: fun0:
; CHECK: # %bb.0:
-; CHECK-NEXT: vlgvf %r1, %v24, 3
-; CHECK-NEXT: vlgvf %r0, %v24, 2
+; CHECK-NEXT: vlgvf %r1, %v24, 0
+; CHECK-NEXT: vlgvf %r0, %v24, 1
; CHECK-NEXT: sllg %r1, %r1, 29
; CHECK-NEXT: rosbg %r1, %r0, 35, 63, 62
; CHECK-NEXT: nihh %r1, 4095
-; CHECK-NEXT: vlgvf %r3, %v24, 0
; CHECK-NEXT: stg %r1, 0(%r2)
-; CHECK-NEXT: vlgvf %r1, %v24, 1
-; CHECK-NEXT: llgtr %r3, %r3
-; CHECK-NEXT: rosbg %r3, %r1, 2, 32, 31
-; CHECK-NEXT: rosbg %r3, %r0, 0, 1, 62
-; CHECK-NEXT: stg %r3, 8(%r2)
+; CHECK-NEXT: vlgvf %r1, %v24, 2
+; CHECK-NEXT: risbgn %r0, %r0, 0, 129, 62
+; CHECK-NEXT: rosbg %r0, %r1, 2, 32, 31
+; CHECK-NEXT: vlgvf %r1, %v24, 3
+; CHECK-NEXT: rosbg %r0, %r1, 33, 63, 0
+; CHECK-NEXT: stg %r0, 8(%r2)
; CHECK-NEXT: br %r14
{
store <4 x i31> %src, <4 x i31>* %p
@@ -31,36 +31,36 @@ define i16 @fun1(<16 x i1> %src)
; CHECK-NEXT: .cfi_def_cfa_offset 328
; CHECK-NEXT: vlgvb %r0, %v24, 0
; CHECK-NEXT: vlgvb %r1, %v24, 1
-; CHECK-NEXT: nilf %r0, 1
-; CHECK-NEXT: rosbg %r0, %r1, 62, 62, 1
+; CHECK-NEXT: risblg %r0, %r0, 16, 144, 15
+; CHECK-NEXT: rosbg %r0, %r1, 49, 49, 14
; CHECK-NEXT: vlgvb %r1, %v24, 2
-; CHECK-NEXT: rosbg %r0, %r1, 61, 61, 2
+; CHECK-NEXT: rosbg %r0, %r1, 50, 50, 13
; CHECK-NEXT: vlgvb %r1, %v24, 3
-; CHECK-NEXT: rosbg %r0, %r1, 60, 60, 3
+; CHECK-NEXT: rosbg %r0, %r1, 51, 51, 12
; CHECK-NEXT: vlgvb %r1, %v24, 4
-; CHECK-NEXT: rosbg %r0, %r1, 59, 59, 4
+; CHECK-NEXT: rosbg %r0, %r1, 52, 52, 11
; CHECK-NEXT: vlgvb %r1, %v24, 5
-; CHECK-NEXT: rosbg %r0, %r1, 58, 58, 5
+; CHECK-NEXT: rosbg %r0, %r1, 53, 53, 10
; CHECK-NEXT: vlgvb %r1, %v24, 6
-; CHECK-NEXT: rosbg %r0, %r1, 57, 57, 6
+; CHECK-NEXT: rosbg %r0, %r1, 54, 54, 9
; CHECK-NEXT: vlgvb %r1, %v24, 7
-; CHECK-NEXT: rosbg %r0, %r1, 56, 56, 7
-; CHECK-NEXT: vlgvb %r1, %v24, 8
; CHECK-NEXT: rosbg %r0, %r1, 55, 55, 8
+; CHECK-NEXT: vlgvb %r1, %v24, 8
+; CHECK-NEXT: rosbg %r0, %r1, 56, 56, 7
; CHECK-NEXT: vlgvb %r1, %v24, 9
-; CHECK-NEXT: rosbg %r0, %r1, 54, 54, 9
+; CHECK-NEXT: rosbg %r0, %r1, 57, 57, 6
; CHECK-NEXT: vlgvb %r1, %v24, 10
-; CHECK-NEXT: rosbg %r0, %r1, 53, 53, 10
+; CHECK-NEXT: rosbg %r0, %r1, 58, 58, 5
; CHECK-NEXT: vlgvb %r1, %v24, 11
-; CHECK-NEXT: rosbg %r0, %r1, 52, 52, 11
+; CHECK-NEXT: rosbg %r0, %r1, 59, 59, 4
; CHECK-NEXT: vlgvb %r1, %v24, 12
-; CHECK-NEXT: rosbg %r0, %r1, 51, 51, 12
+; CHECK-NEXT: rosbg %r0, %r1, 60, 60, 3
; CHECK-NEXT: vlgvb %r1, %v24, 13
-; CHECK-NEXT: rosbg %r0, %r1, 50, 50, 13
+; CHECK-NEXT: rosbg %r0, %r1, 61, 61, 2
; CHECK-NEXT: vlgvb %r1, %v24, 14
-; CHECK-NEXT: rosbg %r0, %r1, 49, 49, 14
+; CHECK-NEXT: rosbg %r0, %r1, 62, 62, 1
; CHECK-NEXT: vlgvb %r1, %v24, 15
-; CHECK-NEXT: rosbg %r0, %r1, 32, 48, 15
+; CHECK-NEXT: rosbg %r0, %r1, 63, 63, 0
; CHECK-NEXT: sth %r0, 160(%r15)
; CHECK-NEXT: lh %r2, 160(%r15)
; CHECK-NEXT: aghi %r15, 168
@@ -77,40 +77,40 @@ define void @fun2(<8 x i32> %src, <8 x i
; CHECK-NEXT: stmg %r14, %r15, 112(%r15)
; CHECK-NEXT: .cfi_offset %r14, -48
; CHECK-NEXT: .cfi_offset %r15, -40
-; CHECK-NEXT: vlgvf %r1, %v24, 0
-; CHECK-NEXT: stc %r1, 30(%r2)
-; CHECK-NEXT: llgtr %r0, %r1
-; CHECK-NEXT: # kill: def $r1l killed $r1l killed $r1d def $r1d
-; CHECK-NEXT: srl %r1, 8
-; CHECK-NEXT: sth %r1, 28(%r2)
+; CHECK-NEXT: vlgvf %r3, %v26, 1
+; CHECK-NEXT: vlgvf %r1, %v26, 2
+; CHECK-NEXT: risbgn %r4, %r3, 0, 129, 62
+; CHECK-NEXT: rosbg %r4, %r1, 2, 32, 31
+; CHECK-NEXT: vlgvf %r0, %v26, 3
+; CHECK-NEXT: rosbg %r4, %r0, 33, 63, 0
+; CHECK-NEXT: stc %r0, 30(%r2)
+; CHECK-NEXT: # kill: def $r0l killed $r0l killed $r0d def $r0d
+; CHECK-NEXT: srl %r0, 8
; CHECK-NEXT: vlgvf %r1, %v24, 1
-; CHECK-NEXT: rosbg %r0, %r1, 2, 32, 31
-; CHECK-NEXT: srlg %r1, %r0, 24
-; CHECK-NEXT: vlgvf %r3, %v26, 0
+; CHECK-NEXT: vlgvf %r14, %v24, 0
+; CHECK-NEXT: sth %r0, 28(%r2)
+; CHECK-NEXT: vlgvf %r0, %v24, 2
+; CHECK-NEXT: risbgn %r5, %r1, 0, 133, 58
+; CHECK-NEXT: rosbg %r5, %r0, 6, 36, 27
+; CHECK-NEXT: sllg %r14, %r14, 25
+; CHECK-NEXT: rosbg %r14, %r1, 39, 63, 58
+; CHECK-NEXT: vlgvf %r0, %v24, 3
+; CHECK-NEXT: rosbg %r5, %r0, 37, 63, 60
+; CHECK-NEXT: sllg %r1, %r14, 8
+; CHECK-NEXT: rosbg %r1, %r5, 56, 63, 8
+; CHECK-NEXT: stg %r1, 0(%r2)
+; CHECK-NEXT: srlg %r1, %r4, 24
; CHECK-NEXT: st %r1, 24(%r2)
-; CHECK-NEXT: vlgvf %r1, %v26, 1
-; CHECK-NEXT: risbgn %r4, %r3, 37, 191, 60
-; CHECK-NEXT: vlgvf %r5, %v26, 3
-; CHECK-NEXT: sllg %r5, %r5, 25
-; CHECK-NEXT: rosbg %r4, %r1, 6, 36, 27
-; CHECK-NEXT: vlgvf %r1, %v26, 2
-; CHECK-NEXT: rosbg %r5, %r1, 39, 63, 58
-; CHECK-NEXT: rosbg %r4, %r1, 0, 5, 58
+; CHECK-NEXT: vlgvf %r1, %v26, 0
+; CHECK-NEXT: risbgn %r0, %r0, 0, 131, 60
+; CHECK-NEXT: rosbg %r0, %r1, 4, 34, 29
; CHECK-NEXT: sllg %r1, %r5, 8
-; CHECK-NEXT: rosbg %r1, %r4, 56, 63, 8
-; CHECK-NEXT: vlgvf %r5, %v24, 2
-; CHECK-NEXT: rosbg %r0, %r5, 0, 1, 62
-; CHECK-NEXT: stg %r1, 0(%r2)
-; CHECK-NEXT: vlgvf %r1, %v24, 3
-; CHECK-NEXT: risbgn %r14, %r5, 35, 191, 62
-; CHECK-NEXT: rosbg %r14, %r1, 4, 34, 29
-; CHECK-NEXT: sllg %r1, %r4, 8
-; CHECK-NEXT: rosbg %r14, %r3, 0, 3, 60
-; CHECK-NEXT: rosbg %r1, %r14, 56, 63, 8
-; CHECK-NEXT: stg %r1, 8(%r2)
-; CHECK-NEXT: sllg %r1, %r14, 8
+; CHECK-NEXT: rosbg %r0, %r3, 35, 63, 62
; CHECK-NEXT: rosbg %r1, %r0, 56, 63, 8
-; CHECK-NEXT: stg %r1, 16(%r2)
+; CHECK-NEXT: stg %r1, 8(%r2)
+; CHECK-NEXT: sllg %r0, %r0, 8
+; CHECK-NEXT: rosbg %r0, %r4, 56, 63, 8
+; CHECK-NEXT: stg %r0, 16(%r2)
; CHECK-NEXT: lmg %r14, %r15, 112(%r15)
; CHECK-NEXT: br %r14
{
@@ -123,17 +123,18 @@ define void @fun2(<8 x i32> %src, <8 x i
define void @fun3(<3 x i31>* %src, <3 x i31>* %p)
; CHECK-LABEL: fun3:
; CHECK: # %bb.0:
-; CHECK-NEXT: llgf %r0, 3(%r2)
; CHECK-NEXT: llgf %r1, 0(%r2)
-; CHECK-NEXT: rosbg %r1, %r0, 0, 32, 31
+; CHECK-NEXT: llgf %r0, 3(%r2)
+; CHECK-NEXT: sllg %r4, %r1, 62
+; CHECK-NEXT: rosbg %r4, %r0, 0, 32, 31
; CHECK-NEXT: llgf %r0, 6(%r2)
-; CHECK-NEXT: st %r1, 8(%r3)
-; CHECK-NEXT: rosbg %r1, %r0, 0, 1, 62
-; CHECK-NEXT: srlg %r1, %r1, 32
-; CHECK-NEXT: sllg %r0, %r0, 30
-; CHECK-NEXT: lr %r0, %r1
-; CHECK-NEXT: nihh %r0, 8191
-; CHECK-NEXT: stg %r0, 0(%r3)
+; CHECK-NEXT: ogr %r0, %r4
+; CHECK-NEXT: st %r0, 8(%r3)
+; CHECK-NEXT: srlg %r0, %r4, 32
+; CHECK-NEXT: sllg %r1, %r1, 30
+; CHECK-NEXT: lr %r1, %r0
+; CHECK-NEXT: nihh %r1, 8191
+; CHECK-NEXT: stg %r1, 0(%r3)
; CHECK-NEXT: br %r14
{
%tmp = load <3 x i31>, <3 x i31>* %src
Modified: llvm/trunk/test/CodeGen/SystemZ/vec-move-17.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/vec-move-17.ll?rev=324063&r1=324062&r2=324063&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/vec-move-17.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/vec-move-17.ll Fri Feb 2 00:48:02 2018
@@ -65,8 +65,9 @@ define void @f7(<2 x i64> %val, <2 x i1>
; CHECK-LABEL: f7:
; CHECK: # %bb.0:
; CHECK-NEXT: vlgvg %r0, %v24, 0
+; CHECK-NEXT: sll %r0, 1
; CHECK-NEXT: vlgvg %r1, %v24, 1
-; CHECK-NEXT: risbgn %r0, %r1, 32, 62, 1
+; CHECK-NEXT: rosbg %r0, %r1, 63, 63, 0
; CHECK-NEXT: nilf %r0, 3
; CHECK-NEXT: stc %r0, 0(%r2)
; CHECK-NEXT: br %r14
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