[llvm] r323955 - [AArch64][NFC] Make all ProcResource definitions include their SchedModel.
Clement Courbet via llvm-commits
llvm-commits at lists.llvm.org
Thu Feb 1 04:12:01 PST 2018
Author: courbet
Date: Thu Feb 1 04:12:01 2018
New Revision: 323955
URL: http://llvm.org/viewvc/llvm-project?rev=323955&view=rev
Log:
[AArch64][NFC] Make all ProcResource definitions include their SchedModel.
This makes targets ExynosM1,ExynosM3,ThunderX2T99 consistent with all
other targets.
Modified:
llvm/trunk/lib/Target/AArch64/AArch64SchedExynosM1.td
llvm/trunk/lib/Target/AArch64/AArch64SchedExynosM3.td
llvm/trunk/lib/Target/AArch64/AArch64SchedThunderX2T99.td
Modified: llvm/trunk/lib/Target/AArch64/AArch64SchedExynosM1.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64SchedExynosM1.td?rev=323955&r1=323954&r2=323955&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64SchedExynosM1.td (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64SchedExynosM1.td Thu Feb 1 04:12:01 2018
@@ -32,6 +32,8 @@ def ExynosM1Model : SchedMachineModel {
// Define each kind of processor resource and number available on the Exynos-M1,
// which has 9 pipelines, each with its own queue with out-of-order dispatch.
+let SchedModel = ExynosM1Model in {
+
def M1UnitA : ProcResource<2>; // Simple integer
def M1UnitC : ProcResource<1>; // Simple and complex integer
def M1UnitD : ProcResource<1>; // Integer division (inside C, serialized)
@@ -54,14 +56,10 @@ let Super = M1PipeF1 in {
def M1UnitFST : ProcResource<1>; // FP store
}
-let SchedModel = ExynosM1Model in {
- def M1UnitALU : ProcResGroup<[M1UnitA,
- M1UnitC]>; // All integer
- def M1UnitNALU : ProcResGroup<[M1UnitNAL0,
- M1UnitNAL1]>; // All simple vector
-}
-
-let SchedModel = ExynosM1Model in {
+def M1UnitALU : ProcResGroup<[M1UnitA,
+ M1UnitC]>; // All integer
+def M1UnitNALU : ProcResGroup<[M1UnitNAL0,
+ M1UnitNAL1]>; // All simple vector
//===----------------------------------------------------------------------===//
// Predicates.
Modified: llvm/trunk/lib/Target/AArch64/AArch64SchedExynosM3.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64SchedExynosM3.td?rev=323955&r1=323954&r2=323955&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64SchedExynosM3.td (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64SchedExynosM3.td Thu Feb 1 04:12:01 2018
@@ -32,6 +32,8 @@ def ExynosM3Model : SchedMachineModel {
// Define each kind of processor resource and number available on the Exynos-M3,
// which has 12 pipelines, each with its own queue with out-of-order dispatch.
+let SchedModel = ExynosM3Model in {
+
def M3UnitA : ProcResource<2>; // Simple integer
def M3UnitC : ProcResource<2>; // Simple and complex integer
def M3UnitD : ProcResource<2>; // Integer division (inside C, serialized)
@@ -74,36 +76,32 @@ let Super = M3PipeF2 in {
def M3UnitNSHF2 : ProcResource<1>; // Vector shuffling
}
-let SchedModel = ExynosM3Model in {
-
- def M3UnitALU : ProcResGroup<[M3UnitA,
- M3UnitC]>;
- def M3UnitFMAC : ProcResGroup<[M3UnitFMAC0,
- M3UnitFMAC1,
- M3UnitFMAC2]>;
- def M3UnitFADD : ProcResGroup<[M3UnitFADD0,
- M3UnitFADD1,
- M3UnitFADD2]>;
- def M3UnitFDIV : ProcResGroup<[M3UnitFDIV0,
- M3UnitFDIV1]>;
- def M3UnitFCVT : ProcResGroup<[M3UnitFCVT0,
- M3UnitFCVT1]>;
- def M3UnitFST : ProcResGroup<[M3UnitFST0,
- M3UnitFST1]>;
- def M3UnitNALU : ProcResGroup<[M3UnitNALU0,
- M3UnitNALU1,
- M3UnitNALU2]>;
- def M3UnitNCRY : ProcResGroup<[M3UnitNCRY0,
- M3UnitNCRY1]>;
- def M3UnitNSHT : ProcResGroup<[M3UnitNSHT0,
- M3UnitNSHT1,
- M3UnitNSHT2]>;
- def M3UnitNSHF : ProcResGroup<[M3UnitNSHF0,
- M3UnitNSHF1,
- M3UnitNSHF2]>;
-}
-let SchedModel = ExynosM3Model in {
+def M3UnitALU : ProcResGroup<[M3UnitA,
+ M3UnitC]>;
+def M3UnitFMAC : ProcResGroup<[M3UnitFMAC0,
+ M3UnitFMAC1,
+ M3UnitFMAC2]>;
+def M3UnitFADD : ProcResGroup<[M3UnitFADD0,
+ M3UnitFADD1,
+ M3UnitFADD2]>;
+def M3UnitFDIV : ProcResGroup<[M3UnitFDIV0,
+ M3UnitFDIV1]>;
+def M3UnitFCVT : ProcResGroup<[M3UnitFCVT0,
+ M3UnitFCVT1]>;
+def M3UnitFST : ProcResGroup<[M3UnitFST0,
+ M3UnitFST1]>;
+def M3UnitNALU : ProcResGroup<[M3UnitNALU0,
+ M3UnitNALU1,
+ M3UnitNALU2]>;
+def M3UnitNCRY : ProcResGroup<[M3UnitNCRY0,
+ M3UnitNCRY1]>;
+def M3UnitNSHT : ProcResGroup<[M3UnitNSHT0,
+ M3UnitNSHT1,
+ M3UnitNSHT2]>;
+def M3UnitNSHF : ProcResGroup<[M3UnitNSHF0,
+ M3UnitNSHF1,
+ M3UnitNSHF2]>;
//===----------------------------------------------------------------------===//
// Predicates.
Modified: llvm/trunk/lib/Target/AArch64/AArch64SchedThunderX2T99.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64SchedThunderX2T99.td?rev=323955&r1=323954&r2=323955&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64SchedThunderX2T99.td (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64SchedThunderX2T99.td Thu Feb 1 04:12:01 2018
@@ -29,6 +29,8 @@ def ThunderX2T99Model : SchedMachineMode
list<Predicate> UnsupportedFeatures = [HasSVE];
}
+let SchedModel = ThunderX2T99Model in {
+
// Define the issue ports.
// Port 0: ALU, FP/SIMD.
@@ -49,8 +51,6 @@ def THX2T99P4 : ProcResource<1>;
// Port 5: Load/store.
def THX2T99P5 : ProcResource<1>;
-let SchedModel = ThunderX2T99Model in {
-
// Define groups for the functional units on each issue port. Each group
// created will be used by a WriteRes later on.
//
@@ -359,13 +359,10 @@ def : ReadAdvance<ReadID, 0>;
def : ReadAdvance<ReadExtrHi, 0>;
def : ReadAdvance<ReadAdrBase, 0>;
def : ReadAdvance<ReadVLD, 0>;
-}
//===----------------------------------------------------------------------===//
// 3. Instruction Tables.
-let SchedModel = ThunderX2T99Model in {
-
//---
// 3.1 Branch Instructions
//---
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