[llvm] r323954 - [ARM] Add support for unpredictable MVN instructions.

[Yvan Roux via llvm-commits]

Author: yroux
Date: Thu Feb  1 04:06:57 2018
New Revision: 323954

URL: http://llvm.org/viewvc/llvm-project?rev=323954&view=rev
Log:
[ARM] Add support for unpredictable MVN instructions.

This fixes bugzilla 33011
https://bugs.llvm.org/show_bug.cgi?id=33011

Defines bits {19-16} as zero or unpredictable as specified by the ARM ARM in
sections A8.8.116 and A8.8.117.

It fixes also the usage of PC register as destination register for MVN
register-shifted register version as specified in A8.8.117.

Differential Revision: https://reviews.llvm.org/D41905

Added:
    llvm/trunk/test/MC/Disassembler/ARM/unpredictable-MVN-arm.txt
Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
    llvm/trunk/test/MC/ARM/diagnostics.s

Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=323954&r1=323953&r2=323954&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Thu Feb  1 04:06:57 2018
@@ -3912,6 +3912,8 @@ def  MVNr  : AsI1<0b1111, (outs GPR:$Rd)
   let Inst{11-4} = 0b00000000;
   let Inst{15-12} = Rd;
   let Inst{3-0} = Rm;
+
+  let Unpredictable{19-16} = 0b1111;
 }
 def  MVNsi  : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_imm:$shift),
                   DPSoRegImmFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift",
@@ -3925,10 +3927,12 @@ def  MVNsi  : AsI1<0b1111, (outs GPR:$Rd
   let Inst{11-5} = shift{11-5};
   let Inst{4} = 0;
   let Inst{3-0} = shift{3-0};
+
+  let Unpredictable{19-16} = 0b1111;
 }
-def  MVNsr  : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_reg:$shift),
+def  MVNsr  : AsI1<0b1111, (outs GPRnopc:$Rd), (ins so_reg_reg:$shift),
                   DPSoRegRegFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift",
-                  [(set GPR:$Rd, (not so_reg_reg:$shift))]>, UnaryDP,
+                  [(set GPRnopc:$Rd, (not so_reg_reg:$shift))]>, UnaryDP,
                   Sched<[WriteALU]> {
   bits<4> Rd;
   bits<12> shift;
@@ -3940,6 +3944,8 @@ def  MVNsr  : AsI1<0b1111, (outs GPR:$Rd
   let Inst{6-5} = shift{6-5};
   let Inst{4} = 1;
   let Inst{3-0} = shift{3-0};
+
+  let Unpredictable{19-16} = 0b1111;
 }
 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
 def  MVNi  : AsI1<0b1111, (outs GPR:$Rd), (ins mod_imm:$imm), DPFrm,

Modified: llvm/trunk/test/MC/ARM/diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/diagnostics.s?rev=323954&r1=323953&r2=323954&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/diagnostics.s (original)
+++ llvm/trunk/test/MC/ARM/diagnostics.s Thu Feb  1 04:06:57 2018
@@ -742,3 +742,10 @@ foo2:
         adds r0
 @ CHECK-ERRORS: error: too few operands for instruction
 @ CHECK-ERRORS: error: too few operands for instruction
+
+        @ Using pc for MVN
+	mvn pc, r6, lsl r7
+@ CHECK-ERRORS: error: invalid instruction, any one of the following would fix this:
+@ CHECK-ERRORS: note: operand must be a register in range [r0, r14]
+@ CHECK-ERRORS:         mvn pc, r6, lsl r7
+@ CHECK-ERRORS:             ^

Added: llvm/trunk/test/MC/Disassembler/ARM/unpredictable-MVN-arm.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/unpredictable-MVN-arm.txt?rev=323954&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/unpredictable-MVN-arm.txt (added)
+++ llvm/trunk/test/MC/Disassembler/ARM/unpredictable-MVN-arm.txt Thu Feb  1 04:06:57 2018
@@ -0,0 +1,38 @@
+# RUN: llvm-mc --disassemble %s -triple=armv7-linux-gnueabi 2>&1 | FileCheck %s
+
+# A8.8.116 MVN (register)
+# MVN(S)<c> <Rd>, <Rm>{, <shift>}
+#
+#  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0
+# -------------------------------------------------------------------------------------------------
+# | cond      | 0  0| 0| 1  1  1  1| S|(0)(0)(0)(0)| Rd       |  imm5        |type | 0| Rm        |
+# -------------------------------------------------------------------------------------------------
+
+# MVN  r2, r3  ; with bit 16 == 1 => Unpredictable
+# CHECK: potentially undefined
+# CHECK: 0x03 0x20 0xe1 0xe1
+0x03 0x20 0xe1 0xe1
+
+# A8.8.117 MVN (register-shifted register)
+# MVN(S)<c> <Rd>, <Rm>, <type> <Rs>
+#
+#  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0
+# -------------------------------------------------------------------------------------------------
+# | cond      | 0  0| 0| 1  1  1  1| S|(0)(0)(0)(0)| Rd       | Rs        | 0|type | 1| Rm        |
+# -------------------------------------------------------------------------------------------------
+# if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;
+
+# MVN  r5, pc, lsl r7
+# CHECK: potentially undefined
+# CHECK: 0x1f 0x57 0xe0 0xe1
+0x1f 0x57 0xe0 0xe1
+
+# MVN  pc, r6, lsl r7
+# CHECK: potentially undefined
+# CHECK: 0x16 0xf7 0xe0 0xe1
+0x16 0xf7 0xe0 0xe1
+
+# MVN  r5, r6, lsl pc
+# CHECK: potentially undefined
+# CHECK: 0x16 0x5f 0xe0 0xe1
+0x16 0x5f 0xe0 0xe1