[llvm] r323732 - [ARM GlobalISel] Add inst selector tests for G_SITOFP and G_UITOFP
Diana Picus via llvm-commits
llvm-commits at lists.llvm.org
Tue Jan 30 01:15:27 PST 2018
Author: rovka
Date: Tue Jan 30 01:15:27 2018
New Revision: 323732
URL: http://llvm.org/viewvc/llvm-project?rev=323732&view=rev
Log:
[ARM GlobalISel] Add inst selector tests for G_SITOFP and G_UITOFP
These are handled by the TableGen'erated code.
Modified:
llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir
Modified: llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir?rev=323732&r1=323731&r2=323732&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir (original)
+++ llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir Tue Jan 30 01:15:27 2018
@@ -38,6 +38,11 @@
define void @test_fptoui_s32() #0 { ret void }
define void @test_fptoui_s64() #0 { ret void }
+ define void @test_sitofp_s32() #0 { ret void }
+ define void @test_sitofp_s64() #0 { ret void }
+ define void @test_uitofp_s32() #0 { ret void }
+ define void @test_uitofp_s64() #0 { ret void }
+
define void @test_sub_s32() { ret void }
define void @test_sub_imm_s32() { ret void }
define void @test_sub_rev_imm_s32() { ret void }
@@ -898,6 +903,114 @@ body: |
; CHECK: BX_RET 14, %noreg, implicit %r0
...
---
+name: test_sitofp_s32
+# CHECK-LABEL: name: test_sitofp_s32
+legalized: true
+regBankSelected: true
+selected: false
+# CHECK: selected: true
+registers:
+ - { id: 0, class: gprb }
+ - { id: 1, class: fprb }
+body: |
+ bb.0:
+ liveins: %r0
+
+ %0(s32) = COPY %r0
+ ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0
+
+ %1(s32) = G_SITOFP %0(s32)
+ ; CHECK: [[VREGF:%[0-9]+]]:spr = COPY [[VREGX]]
+ ; CHECK: [[VREGR:%[0-9]+]]:spr = VSITOS [[VREGF]], 14, %noreg
+
+ %s0 = COPY %1(s32)
+ ; CHECK: %s0 = COPY [[VREGR]]
+
+ BX_RET 14, %noreg, implicit %s0
+ ; CHECK: BX_RET 14, %noreg, implicit %s0
+...
+---
+name: test_sitofp_s64
+# CHECK-LABEL: name: test_sitofp_s64
+legalized: true
+regBankSelected: true
+selected: false
+# CHECK: selected: true
+registers:
+ - { id: 0, class: gprb }
+ - { id: 1, class: fprb }
+body: |
+ bb.0:
+ liveins: %r0
+
+ %0(s32) = COPY %r0
+ ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0
+
+ %1(s64) = G_SITOFP %0(s32)
+ ; CHECK: [[VREGF:%[0-9]+]]:spr = COPY [[VREGX]]
+ ; CHECK: [[VREGR:%[0-9]+]]:dpr = VSITOD [[VREGF]], 14, %noreg
+
+ %d0 = COPY %1(s64)
+ ; CHECK: %d0 = COPY [[VREGR]]
+
+ BX_RET 14, %noreg, implicit %d0
+ ; CHECK: BX_RET 14, %noreg, implicit %d0
+...
+---
+name: test_uitofp_s32
+# CHECK-LABEL: name: test_uitofp_s32
+legalized: true
+regBankSelected: true
+selected: false
+# CHECK: selected: true
+registers:
+ - { id: 0, class: gprb }
+ - { id: 1, class: fprb }
+body: |
+ bb.0:
+ liveins: %r0
+
+ %0(s32) = COPY %r0
+ ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0
+
+ %1(s32) = G_UITOFP %0(s32)
+ ; CHECK: [[VREGF:%[0-9]+]]:spr = COPY [[VREGX]]
+ ; CHECK: [[VREGR:%[0-9]+]]:spr = VUITOS [[VREGF]], 14, %noreg
+
+ %s0 = COPY %1(s32)
+ ; CHECK: %s0 = COPY [[VREGR]]
+
+ BX_RET 14, %noreg, implicit %s0
+ ; CHECK: BX_RET 14, %noreg, implicit %s0
+...
+---
+name: test_uitofp_s64
+# CHECK-LABEL: name: test_uitofp_s64
+legalized: true
+regBankSelected: true
+selected: false
+# CHECK: selected: true
+registers:
+ - { id: 0, class: gprb }
+ - { id: 1, class: fprb }
+body: |
+ bb.0:
+ liveins: %r0
+
+ %0(s32) = COPY %r0
+ ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0
+
+ %1(s64) = G_UITOFP %0(s32)
+ ; CHECK: [[VREGF:%[0-9]+]]:spr = COPY [[VREGX]]
+ ; CHECK: [[VREGR:%[0-9]+]]:dpr = VUITOD [[VREGF]], 14, %noreg
+
+ %d0 = COPY %1(s64)
+ ; CHECK: %d0 = COPY [[VREGR]]
+
+ BX_RET 14, %noreg, implicit %d0
+ ; CHECK: BX_RET 14, %noreg, implicit %d0
+...
+---
name: test_sub_s32
# CHECK-LABEL: name: test_sub_s32
legalized: true
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