[llvm] r323731 - [ARM GlobalISel] Map G_SITOFP and G_UITOFP

[Diana Picus via llvm-commits]

Author: rovka
Date: Tue Jan 30 01:15:23 2018
New Revision: 323731

URL: http://llvm.org/viewvc/llvm-project?rev=323731&view=rev
Log:
[ARM GlobalISel] Map G_SITOFP and G_UITOFP

Straightforward mapping (integer operand to GPR, floating point operand
to FPR).

Modified:
    llvm/trunk/lib/Target/ARM/ARMRegisterBankInfo.cpp
    llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir

Modified: llvm/trunk/lib/Target/ARM/ARMRegisterBankInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMRegisterBankInfo.cpp?rev=323731&r1=323730&r2=323731&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMRegisterBankInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMRegisterBankInfo.cpp Tue Jan 30 01:15:23 2018
@@ -317,6 +317,20 @@ ARMRegisterBankInfo::getInstrMapping(con
                                     &ARM::ValueMappings[ARM::SPR3OpsIdx]});
     break;
   }
+  case G_SITOFP:
+  case G_UITOFP: {
+    LLT ToTy = MRI.getType(MI.getOperand(0).getReg());
+    LLT FromTy = MRI.getType(MI.getOperand(1).getReg());
+    if (FromTy.getSizeInBits() == 32 &&
+        (ToTy.getSizeInBits() == 32 || ToTy.getSizeInBits() == 64))
+      OperandsMapping =
+          ToTy.getSizeInBits() == 64
+              ? getOperandsMapping({&ARM::ValueMappings[ARM::DPR3OpsIdx],
+                                    &ARM::ValueMappings[ARM::GPR3OpsIdx]})
+              : getOperandsMapping({&ARM::ValueMappings[ARM::SPR3OpsIdx],
+                                    &ARM::ValueMappings[ARM::GPR3OpsIdx]});
+    break;
+  }
   case G_CONSTANT:
   case G_FRAME_INDEX:
   case G_GLOBAL_VALUE:

Modified: llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir?rev=323731&r1=323730&r2=323731&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir (original)
+++ llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir Tue Jan 30 01:15:23 2018
@@ -73,6 +73,11 @@
   define void @test_fptoui_s32() #0 { ret void }
   define void @test_fptoui_s64() #0 { ret void }
 
+  define void @test_sitofp_s32() #0 { ret void }
+  define void @test_sitofp_s64() #0 { ret void }
+  define void @test_uitofp_s32() #0 { ret void }
+  define void @test_uitofp_s64() #0 { ret void }
+
   define void @test_soft_fp_s64() #0 { ret void }
 
   attributes #0 = { "target-features"="+vfp2"}
@@ -1334,6 +1339,92 @@ body:             |
     BX_RET 14, %noreg, implicit %r0
 ...
 ---
+name:            test_sitofp_s32
+# CHECK-LABEL: name: test_sitofp_s32
+legalized:       true
+regBankSelected: false
+selected:        false
+# CHECK: registers:
+# CHECK: - { id: 0, class: gprb, preferred-register: '' }
+# CHECK: - { id: 1, class: fprb, preferred-register: '' }
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+body:             |
+  bb.0:
+    liveins: %r0
+
+    %0(s32) = COPY %r0
+    %1(s32) = G_SITOFP %0
+    %s0 = COPY %1(s32)
+    BX_RET 14, %noreg, implicit %s0
+
+...
+---
+name:            test_sitofp_s64
+# CHECK-LABEL: name: test_sitofp_s64
+legalized:       true
+regBankSelected: false
+selected:        false
+# CHECK: registers:
+# CHECK: - { id: 0, class: gprb, preferred-register: '' }
+# CHECK: - { id: 1, class: fprb, preferred-register: '' }
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+body:             |
+  bb.0:
+    liveins: %r0
+
+    %0(s32) = COPY %r0
+    %1(s64) = G_SITOFP %0
+    %d0 = COPY %1(s64)
+    BX_RET 14, %noreg, implicit %d0
+...
+---
+name:            test_uitofp_s32
+# CHECK-LABEL: name: test_uitofp_s32
+legalized:       true
+regBankSelected: false
+selected:        false
+# CHECK: registers:
+# CHECK: - { id: 0, class: gprb, preferred-register: '' }
+# CHECK: - { id: 1, class: fprb, preferred-register: '' }
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+body:             |
+  bb.0:
+    liveins: %r0
+
+    %0(s32) = COPY %r0
+    %1(s32) = G_UITOFP %0
+    %s0 = COPY %1(s32)
+    BX_RET 14, %noreg, implicit %s0
+
+...
+---
+name:            test_uitofp_s64
+# CHECK-LABEL: name: test_uitofp_s64
+legalized:       true
+regBankSelected: false
+selected:        false
+# CHECK: registers:
+# CHECK: - { id: 0, class: gprb, preferred-register: '' }
+# CHECK: - { id: 1, class: fprb, preferred-register: '' }
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+body:             |
+  bb.0:
+    liveins: %r0
+
+    %0(s32) = COPY %r0
+    %1(s64) = G_UITOFP %0
+    %d0 = COPY %1(s64)
+    BX_RET 14, %noreg, implicit %d0
+...
+---
 name:            test_soft_fp_s64
 # CHECK-LABEL: name: test_soft_fp_s64
 legalized:       true