[PATCH] D42580: [ARM] Armv8.2-A FP16 code generation (part 2/3)

[Sjoerd Meijer via Phabricator via llvm-commits]

SjoerdMeijer added a comment.

> Have you tried adding tablegen patterns for bitconvert nodes between i16 and f16? 
>  That's how it currently works for f32<->i32, see the VMOVRS and VMOVSR instructions in ARMInstrVFP.td.

Yes, I've tried that. I think this case is different than VMOVRS because there are no illegal types
involved. We are trying to match something like this:

      t2: i32,ch = CopyFromReg t0, Register:i32 %0
    t7: i16 = truncate t2
  t8: f16 = bitcast t7

and the truncate (as an operand of the bitcast) is legalized to a stack store/load very early because i16
is illegal. Thus, instruction selection never get to see i16 <-> f16 bitcast patterns.
And also, because i16 is illegal, any match rule or rewrite pattern involving i16 is not going to work.
But let me know if I'm missing something here.


https://reviews.llvm.org/D42580