[llvm] r323501 - [X86] Remove LowerVSETCC code for handling vXi1 setcc with vXi8/vXi16 input type. NFC

[Craig Topper via llvm-commits]

Author: ctopper
Date: Thu Jan 25 23:15:17 2018
New Revision: 323501

URL: http://llvm.org/viewvc/llvm-project?rev=323501&view=rev
Log:
[X86] Remove LowerVSETCC code for handling vXi1 setcc with vXi8/vXi16 input type. NFC

These kinds of setccs are promoted by a DAG combine before they ever get to legalization.

Modified:
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=323501&r1=323500&r2=323501&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Thu Jan 25 23:15:17 2018
@@ -17944,12 +17944,9 @@ static SDValue LowerVSETCC(SDValue Op, c
   if (VT.getVectorElementType() == MVT::i1) {
     // In AVX-512 architecture setcc returns mask with i1 elements,
     // But there is no compare instruction for i8 and i16 elements in KNL.
-    // In this case use SSE compare
-    if (OpVT.getScalarSizeInBits() >= 32 || Subtarget.hasBWI())
-      return LowerIntVSETCC_AVX512(Op, DAG);
-
-    return DAG.getNode(ISD::TRUNCATE, dl, VT,
-                        DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
+    assert((OpVT.getScalarSizeInBits() >= 32 || Subtarget.hasBWI()) &&
+           "Unexpected operand type");
+    return LowerIntVSETCC_AVX512(Op, DAG);
   }
 
   // Lower using XOP integer comparisons.