[PATCH] D42536: [AggresiveInstCombine] Added support of select and ShuffleVector to TruncInstCombine expression pattern

[Sanjay Patel via Phabricator via llvm-commits]

spatel added a comment.

In https://reviews.llvm.org/D42536#988277, @aaboud wrote:

>   define void @multi_uses_add(i32 %X, i32 %Y) {
>     %Ax = zext i32 %X to i64
>     %Ay = zext i32 %Y to i64
>     %B = add i64 %Ax, %Ay
>     %C = mul i64 %B, %Ax
>     %T = trunc i64 %C to i32
>     call i32 @use32(i32 %T)
>     ret void
>   }
>


That's too easy - instcombine gets that. I think you need at least one more intermediate binop to show a case that instcombine can't handle.

We need to make sure aggressive-instcombine is showing its unique capability in each test. If you agree that the case with a repeated op is just an oversight for instcombine, lets:

1. Move the existing tests over to instcombine
2. Fix instcombine
3. Add more complex tests for aggressive-instcombine's current functionality
4. Enhance aggressive-instcombine for more opcodes/patterns.


https://reviews.llvm.org/D42536