[PATCH] D42536: [AggresiveInstCombine] Added support of select and ShuffleVector to TruncInstCombine expression pattern

[Amjad Aboud via Phabricator via llvm-commits]

aaboud added a comment.

In https://reviews.llvm.org/D42536#988261, @spatel wrote:

> I apologize for not noticing this before, but do all of the tests here fail in regular instcombine because there's an instruction that uses the same value more than once? Or are there more complicated patterns?


Maybe, the test I added are for the simple case, but there are more complicated cases.
Consider this example:

  define void @multi_uses_add(i32 %X, i32 %Y) {
    %Ax = zext i32 %X to i64
    %Ay = zext i32 %Y to i64
    %B = add i64 %Ax, %Ay
    %C = mul i64 %B, %Ax
    %T = trunc i64 %C to i32
    call i32 @use32(i32 %T)
    ret void
  }

Also, remember that I will be adding the PHINode, in the coming patches, then we need to handle this case:

      A
   /     \
  B       C
   \     /
   PHINode


https://reviews.llvm.org/D42536