[PATCH] D41651: AMDGPU: Add 32-bit constant address space

[Marek Olšák via Phabricator via llvm-commits]

mareko updated this revision to Diff 131490.
mareko added a comment.

Only scalar loads support 32-bit pointers. An address in a VGPR will
fail to compile. That's OK because the results of loads will only be used
in places where VGPRs are forbidden.

Updated AMDGPUAliasAnalysis and used SReg_64_XEXEC.
The tests cover all uses cases we need for Mesa.

Updated documentation.


Repository:
  rL LLVM

https://reviews.llvm.org/D41651

Files:
  docs/AMDGPUUsage.rst
  lib/Target/AMDGPU/AMDGPU.h
  lib/Target/AMDGPU/AMDGPUAliasAnalysis.cpp
  lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp
  lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
  lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
  lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
  lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
  lib/Target/AMDGPU/SIISelLowering.cpp
  lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
  lib/Target/AMDGPU/SIMachineFunctionInfo.h
  lib/Target/AMDGPU/SMInstructions.td
  lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
  test/CodeGen/AMDGPU/constant-address-space-32bit.ll

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