[llvm] r323403 - [X86] Name the MMX phaddd instruction with 3 Ds instead of just 2. NFC
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Wed Jan 24 20:45:32 PST 2018
Author: ctopper
Date: Wed Jan 24 20:45:32 2018
New Revision: 323403
URL: http://llvm.org/viewvc/llvm-project?rev=323403&view=rev
Log:
[X86] Name the MMX phaddd instruction with 3 Ds instead of just 2. NFC
Modified:
llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
llvm/trunk/lib/Target/X86/X86InstrMMX.td
llvm/trunk/lib/Target/X86/X86SchedBroadwell.td
llvm/trunk/lib/Target/X86/X86SchedHaswell.td
llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td
llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td
llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td
llvm/trunk/lib/Target/X86/X86ScheduleZnver1.td
Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=323403&r1=323402&r2=323403&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Wed Jan 24 20:45:32 2018
@@ -1424,9 +1424,9 @@ X86InstrInfo::X86InstrInfo(X86Subtarget
{ X86::MMX_PCMPGTBirr, X86::MMX_PCMPGTBirm, 0 },
{ X86::MMX_PCMPGTDirr, X86::MMX_PCMPGTDirm, 0 },
{ X86::MMX_PCMPGTWirr, X86::MMX_PCMPGTWirm, 0 },
+ { X86::MMX_PHADDDrr, X86::MMX_PHADDDrm, 0 },
{ X86::MMX_PHADDSWrr, X86::MMX_PHADDSWrm, 0 },
{ X86::MMX_PHADDWrr, X86::MMX_PHADDWrm, 0 },
- { X86::MMX_PHADDrr, X86::MMX_PHADDrm, 0 },
{ X86::MMX_PHSUBDrr, X86::MMX_PHSUBDrm, 0 },
{ X86::MMX_PHSUBSWrr, X86::MMX_PHSUBSWrm, 0 },
{ X86::MMX_PHSUBWrr, X86::MMX_PHSUBWrm, 0 },
Modified: llvm/trunk/lib/Target/X86/X86InstrMMX.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrMMX.td?rev=323403&r1=323402&r2=323403&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrMMX.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrMMX.td Wed Jan 24 20:45:32 2018
@@ -388,7 +388,7 @@ defm MMX_PADDUSW : MMXI_binop_rm_int<0xD
defm MMX_PHADDW : SS3I_binop_rm_int_mm<0x01, "phaddw", int_x86_ssse3_phadd_w,
MMX_PHADDSUBW>;
-defm MMX_PHADD : SS3I_binop_rm_int_mm<0x02, "phaddd", int_x86_ssse3_phadd_d,
+defm MMX_PHADDD : SS3I_binop_rm_int_mm<0x02, "phaddd", int_x86_ssse3_phadd_d,
MMX_PHADDSUBD>;
defm MMX_PHADDSW : SS3I_binop_rm_int_mm<0x03, "phaddsw",int_x86_ssse3_phadd_sw,
MMX_PHADDSUBW>;
Modified: llvm/trunk/lib/Target/X86/X86SchedBroadwell.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedBroadwell.td?rev=323403&r1=323402&r2=323403&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedBroadwell.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedBroadwell.td Wed Jan 24 20:45:32 2018
@@ -1378,9 +1378,9 @@ def BWWriteResGroup32 : SchedWriteRes<[B
let NumMicroOps = 3;
let ResourceCycles = [2,1];
}
+def: InstRW<[BWWriteResGroup32], (instregex "MMX_PHADDDrr")>;
def: InstRW<[BWWriteResGroup32], (instregex "MMX_PHADDSWrr")>;
def: InstRW<[BWWriteResGroup32], (instregex "MMX_PHADDWrr")>;
-def: InstRW<[BWWriteResGroup32], (instregex "MMX_PHADDrr")>;
def: InstRW<[BWWriteResGroup32], (instregex "MMX_PHSUBDrr")>;
def: InstRW<[BWWriteResGroup32], (instregex "MMX_PHSUBSWrr")>;
def: InstRW<[BWWriteResGroup32], (instregex "MMX_PHSUBWrr")>;
@@ -2709,9 +2709,9 @@ def BWWriteResGroup96 : SchedWriteRes<[B
let NumMicroOps = 4;
let ResourceCycles = [2,1,1];
}
+def: InstRW<[BWWriteResGroup96], (instregex "MMX_PHADDDrm")>;
def: InstRW<[BWWriteResGroup96], (instregex "MMX_PHADDSWrm")>;
def: InstRW<[BWWriteResGroup96], (instregex "MMX_PHADDWrm")>;
-def: InstRW<[BWWriteResGroup96], (instregex "MMX_PHADDrm")>;
def: InstRW<[BWWriteResGroup96], (instregex "MMX_PHSUBDrm")>;
def: InstRW<[BWWriteResGroup96], (instregex "MMX_PHSUBSWrm")>;
def: InstRW<[BWWriteResGroup96], (instregex "MMX_PHSUBWrm")>;
Modified: llvm/trunk/lib/Target/X86/X86SchedHaswell.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedHaswell.td?rev=323403&r1=323402&r2=323403&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedHaswell.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedHaswell.td Wed Jan 24 20:45:32 2018
@@ -2741,9 +2741,9 @@ def HWWriteResGroup56 : SchedWriteRes<[H
let NumMicroOps = 3;
let ResourceCycles = [2,1];
}
+def: InstRW<[HWWriteResGroup56], (instregex "MMX_PHADDDrr")>;
def: InstRW<[HWWriteResGroup56], (instregex "MMX_PHADDSWrr")>;
def: InstRW<[HWWriteResGroup56], (instregex "MMX_PHADDWrr")>;
-def: InstRW<[HWWriteResGroup56], (instregex "MMX_PHADDrr")>;
def: InstRW<[HWWriteResGroup56], (instregex "MMX_PHSUBDrr")>;
def: InstRW<[HWWriteResGroup56], (instregex "MMX_PHSUBSWrr")>;
def: InstRW<[HWWriteResGroup56], (instregex "MMX_PHSUBWrr")>;
@@ -2857,9 +2857,9 @@ def HWWriteResGroup64 : SchedWriteRes<[H
let NumMicroOps = 4;
let ResourceCycles = [2,1,1];
}
+def: InstRW<[HWWriteResGroup64], (instregex "MMX_PHADDDrm")>;
def: InstRW<[HWWriteResGroup64], (instregex "MMX_PHADDSWrm")>;
def: InstRW<[HWWriteResGroup64], (instregex "MMX_PHADDWrm")>;
-def: InstRW<[HWWriteResGroup64], (instregex "MMX_PHADDrm")>;
def: InstRW<[HWWriteResGroup64], (instregex "MMX_PHSUBDrm")>;
def: InstRW<[HWWriteResGroup64], (instregex "MMX_PHSUBSWrm")>;
def: InstRW<[HWWriteResGroup64], (instregex "MMX_PHSUBWrm")>;
Modified: llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td?rev=323403&r1=323402&r2=323403&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td Wed Jan 24 20:45:32 2018
@@ -1043,9 +1043,9 @@ def SBWriteResGroup24 : SchedWriteRes<[S
let NumMicroOps = 3;
let ResourceCycles = [3];
}
+def: InstRW<[SBWriteResGroup24], (instregex "MMX_PHADDDrr")>;
def: InstRW<[SBWriteResGroup24], (instregex "MMX_PHADDSWrr")>;
def: InstRW<[SBWriteResGroup24], (instregex "MMX_PHADDWrr")>;
-def: InstRW<[SBWriteResGroup24], (instregex "MMX_PHADDrr")>;
def: InstRW<[SBWriteResGroup24], (instregex "MMX_PHSUBDrr")>;
def: InstRW<[SBWriteResGroup24], (instregex "MMX_PHSUBSWrr")>;
def: InstRW<[SBWriteResGroup24], (instregex "MMX_PHSUBWrr")>;
@@ -2066,9 +2066,9 @@ def SBWriteResGroup80 : SchedWriteRes<[S
let NumMicroOps = 4;
let ResourceCycles = [1,3];
}
+def: InstRW<[SBWriteResGroup80], (instregex "MMX_PHADDDrm")>;
def: InstRW<[SBWriteResGroup80], (instregex "MMX_PHADDSWrm")>;
def: InstRW<[SBWriteResGroup80], (instregex "MMX_PHADDWrm")>;
-def: InstRW<[SBWriteResGroup80], (instregex "MMX_PHADDrm")>;
def: InstRW<[SBWriteResGroup80], (instregex "MMX_PHSUBDrm")>;
def: InstRW<[SBWriteResGroup80], (instregex "MMX_PHSUBSWrm")>;
def: InstRW<[SBWriteResGroup80], (instregex "MMX_PHSUBWrm")>;
Modified: llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td?rev=323403&r1=323402&r2=323403&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td Wed Jan 24 20:45:32 2018
@@ -1367,8 +1367,8 @@ def SKLWriteResGroup37 : SchedWriteRes<[
let NumMicroOps = 3;
let ResourceCycles = [2,1];
}
+def: InstRW<[SKLWriteResGroup37], (instregex "MMX_PHADDDrr")>;
def: InstRW<[SKLWriteResGroup37], (instregex "MMX_PHADDWrr")>;
-def: InstRW<[SKLWriteResGroup37], (instregex "MMX_PHADDrr")>;
def: InstRW<[SKLWriteResGroup37], (instregex "MMX_PHSUBDrr")>;
def: InstRW<[SKLWriteResGroup37], (instregex "MMX_PHSUBWrr")>;
@@ -2765,8 +2765,8 @@ def SKLWriteResGroup113 : SchedWriteRes<
let NumMicroOps = 4;
let ResourceCycles = [2,1,1];
}
+def: InstRW<[SKLWriteResGroup113], (instregex "MMX_PHADDDrm")>;
def: InstRW<[SKLWriteResGroup113], (instregex "MMX_PHADDWrm")>;
-def: InstRW<[SKLWriteResGroup113], (instregex "MMX_PHADDrm")>;
def: InstRW<[SKLWriteResGroup113], (instregex "MMX_PHSUBDrm")>;
def: InstRW<[SKLWriteResGroup113], (instregex "MMX_PHSUBWrm")>;
Modified: llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td?rev=323403&r1=323402&r2=323403&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td Wed Jan 24 20:45:32 2018
@@ -2173,8 +2173,8 @@ def SKXWriteResGroup39 : SchedWriteRes<[
let NumMicroOps = 3;
let ResourceCycles = [2,1];
}
+def: InstRW<[SKXWriteResGroup39], (instregex "MMX_PHADDDrr")>;
def: InstRW<[SKXWriteResGroup39], (instregex "MMX_PHADDWrr")>;
-def: InstRW<[SKXWriteResGroup39], (instregex "MMX_PHADDrr")>;
def: InstRW<[SKXWriteResGroup39], (instregex "MMX_PHSUBDrr")>;
def: InstRW<[SKXWriteResGroup39], (instregex "MMX_PHSUBWrr")>;
@@ -4534,8 +4534,8 @@ def SKXWriteResGroup124 : SchedWriteRes<
let NumMicroOps = 4;
let ResourceCycles = [2,1,1];
}
+def: InstRW<[SKXWriteResGroup124], (instregex "MMX_PHADDDrm")>;
def: InstRW<[SKXWriteResGroup124], (instregex "MMX_PHADDWrm")>;
-def: InstRW<[SKXWriteResGroup124], (instregex "MMX_PHADDrm")>;
def: InstRW<[SKXWriteResGroup124], (instregex "MMX_PHSUBDrm")>;
def: InstRW<[SKXWriteResGroup124], (instregex "MMX_PHSUBWrm")>;
Modified: llvm/trunk/lib/Target/X86/X86ScheduleZnver1.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ScheduleZnver1.td?rev=323403&r1=323402&r2=323403&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ScheduleZnver1.td (original)
+++ llvm/trunk/lib/Target/X86/X86ScheduleZnver1.td Wed Jan 24 20:45:32 2018
@@ -1067,7 +1067,7 @@ def : InstRW<[WriteMicrocoded], (instreg
// HADD, HSUB PS/PD
// PHADD|PHSUB (S) W/D.
-def : InstRW<[WriteMicrocoded], (instregex "MMX_PHADD(W?)r(r|m)",
+def : InstRW<[WriteMicrocoded], (instregex "MMX_PHADD(W|D)r(r|m)",
"MMX_PHADDSWr(r|m)",
"MMX_PHSUB(W|D)r(r|m)",
"MMX_PHSUBSWrr",
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