[llvm] r323402 - [X86] Remove 64/128/256 from MMX/SSE/AVX instruction names for overall consistency. NFC
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Wed Jan 24 20:45:30 PST 2018
Author: ctopper
Date: Wed Jan 24 20:45:30 2018
New Revision: 323402
URL: http://llvm.org/viewvc/llvm-project?rev=323402&view=rev
Log:
[X86] Remove 64/128/256 from MMX/SSE/AVX instruction names for overall consistency. NFC
MMX instrutions all start with MMX_ so the 64 isn't needed for disambigutation.
SSE/AVX1 instructions are assumed 128-bit so we don't need to say 128.
AVX2 instructions should use a Y to indicate 256-bits.
Modified:
llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
llvm/trunk/lib/Target/X86/X86InstrMMX.td
llvm/trunk/lib/Target/X86/X86InstrSSE.td
llvm/trunk/lib/Target/X86/X86SchedBroadwell.td
llvm/trunk/lib/Target/X86/X86SchedHaswell.td
llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td
llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td
llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td
llvm/trunk/lib/Target/X86/X86ScheduleZnver1.td
llvm/trunk/test/MC/X86/x86_64-asm-match.s
Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=323402&r1=323401&r2=323402&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Wed Jan 24 20:45:30 2018
@@ -635,7 +635,7 @@ X86InstrInfo::X86InstrInfo(X86Subtarget
{ X86::PCMPESTRM128rr, X86::PCMPESTRM128rm, TB_ALIGN_16 },
{ X86::PCMPISTRIrr, X86::PCMPISTRIrm, TB_ALIGN_16 },
{ X86::PCMPISTRM128rr, X86::PCMPISTRM128rm, TB_ALIGN_16 },
- { X86::PHMINPOSUWrr128, X86::PHMINPOSUWrm128, TB_ALIGN_16 },
+ { X86::PHMINPOSUWrr, X86::PHMINPOSUWrm, TB_ALIGN_16 },
{ X86::PMOVSXBDrr, X86::PMOVSXBDrm, TB_NO_REVERSE },
{ X86::PMOVSXBQrr, X86::PMOVSXBQrm, TB_NO_REVERSE },
{ X86::PMOVSXBWrr, X86::PMOVSXBWrm, TB_NO_REVERSE },
@@ -681,9 +681,9 @@ X86InstrInfo::X86InstrInfo(X86Subtarget
{ X86::MMX_CVTTPD2PIirr, X86::MMX_CVTTPD2PIirm, TB_ALIGN_16 },
{ X86::MMX_CVTTPS2PIirr, X86::MMX_CVTTPS2PIirm, TB_NO_REVERSE },
{ X86::MMX_MOVD64to64rr, X86::MMX_MOVQ64rm, 0 },
- { X86::MMX_PABSBrr64, X86::MMX_PABSBrm64, 0 },
- { X86::MMX_PABSDrr64, X86::MMX_PABSDrm64, 0 },
- { X86::MMX_PABSWrr64, X86::MMX_PABSWrm64, 0 },
+ { X86::MMX_PABSBrr, X86::MMX_PABSBrm, 0 },
+ { X86::MMX_PABSDrr, X86::MMX_PABSDrm, 0 },
+ { X86::MMX_PABSWrr, X86::MMX_PABSWrm, 0 },
{ X86::MMX_PSHUFWri, X86::MMX_PSHUFWmi, 0 },
// 3DNow! version of foldable instructions
@@ -739,7 +739,7 @@ X86InstrInfo::X86InstrInfo(X86Subtarget
{ X86::VPCMPESTRM128rr, X86::VPCMPESTRM128rm, 0 },
{ X86::VPCMPISTRIrr, X86::VPCMPISTRIrm, 0 },
{ X86::VPCMPISTRM128rr, X86::VPCMPISTRM128rm, 0 },
- { X86::VPHMINPOSUWrr128, X86::VPHMINPOSUWrm128, 0 },
+ { X86::VPHMINPOSUWrr, X86::VPHMINPOSUWrm, 0 },
{ X86::VPERMILPDri, X86::VPERMILPDmi, 0 },
{ X86::VPERMILPSri, X86::VPERMILPSmi, 0 },
{ X86::VPMOVSXBDrr, X86::VPMOVSXBDrm, TB_NO_REVERSE },
@@ -1310,9 +1310,9 @@ X86InstrInfo::X86InstrInfo(X86Subtarget
{ X86::PCMPGTWrr, X86::PCMPGTWrm, TB_ALIGN_16 },
{ X86::PHADDDrr, X86::PHADDDrm, TB_ALIGN_16 },
{ X86::PHADDWrr, X86::PHADDWrm, TB_ALIGN_16 },
- { X86::PHADDSWrr128, X86::PHADDSWrm128, TB_ALIGN_16 },
+ { X86::PHADDSWrr, X86::PHADDSWrm, TB_ALIGN_16 },
{ X86::PHSUBDrr, X86::PHSUBDrm, TB_ALIGN_16 },
- { X86::PHSUBSWrr128, X86::PHSUBSWrm128, TB_ALIGN_16 },
+ { X86::PHSUBSWrr, X86::PHSUBSWrm, TB_ALIGN_16 },
{ X86::PHSUBWrr, X86::PHSUBWrm, TB_ALIGN_16 },
{ X86::PINSRBrr, X86::PINSRBrm, 0 },
{ X86::PINSRDrr, X86::PINSRDrm, 0 },
@@ -1342,9 +1342,9 @@ X86InstrInfo::X86InstrInfo(X86Subtarget
{ X86::PORrr, X86::PORrm, TB_ALIGN_16 },
{ X86::PSADBWrr, X86::PSADBWrm, TB_ALIGN_16 },
{ X86::PSHUFBrr, X86::PSHUFBrm, TB_ALIGN_16 },
- { X86::PSIGNBrr128, X86::PSIGNBrm128, TB_ALIGN_16 },
- { X86::PSIGNWrr128, X86::PSIGNWrm128, TB_ALIGN_16 },
- { X86::PSIGNDrr128, X86::PSIGNDrm128, TB_ALIGN_16 },
+ { X86::PSIGNBrr, X86::PSIGNBrm, TB_ALIGN_16 },
+ { X86::PSIGNWrr, X86::PSIGNWrm, TB_ALIGN_16 },
+ { X86::PSIGNDrr, X86::PSIGNDrm, TB_ALIGN_16 },
{ X86::PSLLDrr, X86::PSLLDrm, TB_ALIGN_16 },
{ X86::PSLLQrr, X86::PSLLQrm, TB_ALIGN_16 },
{ X86::PSLLWrr, X86::PSLLWrm, TB_ALIGN_16 },
@@ -1413,7 +1413,7 @@ X86InstrInfo::X86InstrInfo(X86Subtarget
{ X86::MMX_PADDUSBirr, X86::MMX_PADDUSBirm, 0 },
{ X86::MMX_PADDUSWirr, X86::MMX_PADDUSWirm, 0 },
{ X86::MMX_PADDWirr, X86::MMX_PADDWirm, 0 },
- { X86::MMX_PALIGNR64irr, X86::MMX_PALIGNR64irm, 0 },
+ { X86::MMX_PALIGNRrri, X86::MMX_PALIGNRrmi, 0 },
{ X86::MMX_PANDNirr, X86::MMX_PANDNirm, 0 },
{ X86::MMX_PANDirr, X86::MMX_PANDirm, 0 },
{ X86::MMX_PAVGBirr, X86::MMX_PAVGBirm, 0 },
@@ -1424,30 +1424,30 @@ X86InstrInfo::X86InstrInfo(X86Subtarget
{ X86::MMX_PCMPGTBirr, X86::MMX_PCMPGTBirm, 0 },
{ X86::MMX_PCMPGTDirr, X86::MMX_PCMPGTDirm, 0 },
{ X86::MMX_PCMPGTWirr, X86::MMX_PCMPGTWirm, 0 },
- { X86::MMX_PHADDSWrr64, X86::MMX_PHADDSWrm64, 0 },
- { X86::MMX_PHADDWrr64, X86::MMX_PHADDWrm64, 0 },
- { X86::MMX_PHADDrr64, X86::MMX_PHADDrm64, 0 },
- { X86::MMX_PHSUBDrr64, X86::MMX_PHSUBDrm64, 0 },
- { X86::MMX_PHSUBSWrr64, X86::MMX_PHSUBSWrm64, 0 },
- { X86::MMX_PHSUBWrr64, X86::MMX_PHSUBWrm64, 0 },
+ { X86::MMX_PHADDSWrr, X86::MMX_PHADDSWrm, 0 },
+ { X86::MMX_PHADDWrr, X86::MMX_PHADDWrm, 0 },
+ { X86::MMX_PHADDrr, X86::MMX_PHADDrm, 0 },
+ { X86::MMX_PHSUBDrr, X86::MMX_PHSUBDrm, 0 },
+ { X86::MMX_PHSUBSWrr, X86::MMX_PHSUBSWrm, 0 },
+ { X86::MMX_PHSUBWrr, X86::MMX_PHSUBWrm, 0 },
{ X86::MMX_PINSRWrr, X86::MMX_PINSRWrm, 0 },
- { X86::MMX_PMADDUBSWrr64, X86::MMX_PMADDUBSWrm64, 0 },
+ { X86::MMX_PMADDUBSWrr, X86::MMX_PMADDUBSWrm, 0 },
{ X86::MMX_PMADDWDirr, X86::MMX_PMADDWDirm, 0 },
{ X86::MMX_PMAXSWirr, X86::MMX_PMAXSWirm, 0 },
{ X86::MMX_PMAXUBirr, X86::MMX_PMAXUBirm, 0 },
{ X86::MMX_PMINSWirr, X86::MMX_PMINSWirm, 0 },
{ X86::MMX_PMINUBirr, X86::MMX_PMINUBirm, 0 },
- { X86::MMX_PMULHRSWrr64, X86::MMX_PMULHRSWrm64, 0 },
+ { X86::MMX_PMULHRSWrr, X86::MMX_PMULHRSWrm, 0 },
{ X86::MMX_PMULHUWirr, X86::MMX_PMULHUWirm, 0 },
{ X86::MMX_PMULHWirr, X86::MMX_PMULHWirm, 0 },
{ X86::MMX_PMULLWirr, X86::MMX_PMULLWirm, 0 },
{ X86::MMX_PMULUDQirr, X86::MMX_PMULUDQirm, 0 },
{ X86::MMX_PORirr, X86::MMX_PORirm, 0 },
{ X86::MMX_PSADBWirr, X86::MMX_PSADBWirm, 0 },
- { X86::MMX_PSHUFBrr64, X86::MMX_PSHUFBrm64, 0 },
- { X86::MMX_PSIGNBrr64, X86::MMX_PSIGNBrm64, 0 },
- { X86::MMX_PSIGNDrr64, X86::MMX_PSIGNDrm64, 0 },
- { X86::MMX_PSIGNWrr64, X86::MMX_PSIGNWrm64, 0 },
+ { X86::MMX_PSHUFBrr, X86::MMX_PSHUFBrm, 0 },
+ { X86::MMX_PSIGNBrr, X86::MMX_PSIGNBrm, 0 },
+ { X86::MMX_PSIGNDrr, X86::MMX_PSIGNDrm, 0 },
+ { X86::MMX_PSIGNWrr, X86::MMX_PSIGNWrm, 0 },
{ X86::MMX_PSLLDrr, X86::MMX_PSLLDrm, 0 },
{ X86::MMX_PSLLQrr, X86::MMX_PSLLQrm, 0 },
{ X86::MMX_PSLLWrr, X86::MMX_PSLLWrm, 0 },
@@ -1593,10 +1593,10 @@ X86InstrInfo::X86InstrInfo(X86Subtarget
{ X86::VPCMPGTQrr, X86::VPCMPGTQrm, 0 },
{ X86::VPCMPGTWrr, X86::VPCMPGTWrm, 0 },
{ X86::VPHADDDrr, X86::VPHADDDrm, 0 },
- { X86::VPHADDSWrr128, X86::VPHADDSWrm128, 0 },
+ { X86::VPHADDSWrr, X86::VPHADDSWrm, 0 },
{ X86::VPHADDWrr, X86::VPHADDWrm, 0 },
{ X86::VPHSUBDrr, X86::VPHSUBDrm, 0 },
- { X86::VPHSUBSWrr128, X86::VPHSUBSWrm128, 0 },
+ { X86::VPHSUBSWrr, X86::VPHSUBSWrm, 0 },
{ X86::VPHSUBWrr, X86::VPHSUBWrm, 0 },
{ X86::VPERMILPDrr, X86::VPERMILPDrm, 0 },
{ X86::VPERMILPSrr, X86::VPERMILPSrm, 0 },
@@ -1628,9 +1628,9 @@ X86InstrInfo::X86InstrInfo(X86Subtarget
{ X86::VPORrr, X86::VPORrm, 0 },
{ X86::VPSADBWrr, X86::VPSADBWrm, 0 },
{ X86::VPSHUFBrr, X86::VPSHUFBrm, 0 },
- { X86::VPSIGNBrr128, X86::VPSIGNBrm128, 0 },
- { X86::VPSIGNWrr128, X86::VPSIGNWrm128, 0 },
- { X86::VPSIGNDrr128, X86::VPSIGNDrm128, 0 },
+ { X86::VPSIGNBrr, X86::VPSIGNBrm, 0 },
+ { X86::VPSIGNWrr, X86::VPSIGNWrm, 0 },
+ { X86::VPSIGNDrr, X86::VPSIGNDrm, 0 },
{ X86::VPSLLDrr, X86::VPSLLDrm, 0 },
{ X86::VPSLLQrr, X86::VPSLLQrm, 0 },
{ X86::VPSLLWrr, X86::VPSLLWrm, 0 },
@@ -1767,10 +1767,10 @@ X86InstrInfo::X86InstrInfo(X86Subtarget
{ X86::VPERMDYrr, X86::VPERMDYrm, 0 },
{ X86::VPERMPSYrr, X86::VPERMPSYrm, 0 },
{ X86::VPHADDDYrr, X86::VPHADDDYrm, 0 },
- { X86::VPHADDSWrr256, X86::VPHADDSWrm256, 0 },
+ { X86::VPHADDSWYrr, X86::VPHADDSWYrm, 0 },
{ X86::VPHADDWYrr, X86::VPHADDWYrm, 0 },
{ X86::VPHSUBDYrr, X86::VPHSUBDYrm, 0 },
- { X86::VPHSUBSWrr256, X86::VPHSUBSWrm256, 0 },
+ { X86::VPHSUBSWYrr, X86::VPHSUBSWYrm, 0 },
{ X86::VPHSUBWYrr, X86::VPHSUBWYrm, 0 },
{ X86::VPMADDUBSWYrr, X86::VPMADDUBSWYrm, 0 },
{ X86::VPMADDWDYrr, X86::VPMADDWDYrm, 0 },
@@ -1797,9 +1797,9 @@ X86InstrInfo::X86InstrInfo(X86Subtarget
{ X86::VPORYrr, X86::VPORYrm, 0 },
{ X86::VPSADBWYrr, X86::VPSADBWYrm, 0 },
{ X86::VPSHUFBYrr, X86::VPSHUFBYrm, 0 },
- { X86::VPSIGNBYrr256, X86::VPSIGNBYrm256, 0 },
- { X86::VPSIGNWYrr256, X86::VPSIGNWYrm256, 0 },
- { X86::VPSIGNDYrr256, X86::VPSIGNDYrm256, 0 },
+ { X86::VPSIGNBYrr, X86::VPSIGNBYrm, 0 },
+ { X86::VPSIGNWYrr, X86::VPSIGNWYrm, 0 },
+ { X86::VPSIGNDYrr, X86::VPSIGNDYrm, 0 },
{ X86::VPSLLDYrr, X86::VPSLLDYrm, 0 },
{ X86::VPSLLQYrr, X86::VPSLLQYrm, 0 },
{ X86::VPSLLWYrr, X86::VPSLLWYrm, 0 },
Modified: llvm/trunk/lib/Target/X86/X86InstrMMX.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrMMX.td?rev=323402&r1=323401&r2=323402&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrMMX.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrMMX.td Wed Jan 24 20:45:30 2018
@@ -145,16 +145,16 @@ let Constraints = "$src1 = $dst" in {
/// Unary MMX instructions requiring SSSE3.
multiclass SS3I_unop_rm_int_mm<bits<8> opc, string OpcodeStr,
Intrinsic IntId64, OpndItins itins> {
- def rr64 : MMXSS38I<opc, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src),
- !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
- [(set VR64:$dst, (IntId64 VR64:$src))], itins.rr>,
- Sched<[itins.Sched]>;
-
- def rm64 : MMXSS38I<opc, MRMSrcMem, (outs VR64:$dst), (ins i64mem:$src),
- !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
- [(set VR64:$dst,
- (IntId64 (bitconvert (load_mmx addr:$src))))],
- itins.rm>, Sched<[itins.Sched.Folded]>;
+ def rr : MMXSS38I<opc, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src),
+ !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
+ [(set VR64:$dst, (IntId64 VR64:$src))], itins.rr>,
+ Sched<[itins.Sched]>;
+
+ def rm : MMXSS38I<opc, MRMSrcMem, (outs VR64:$dst), (ins i64mem:$src),
+ !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
+ [(set VR64:$dst,
+ (IntId64 (bitconvert (load_mmx addr:$src))))],
+ itins.rm>, Sched<[itins.Sched.Folded]>;
}
/// Binary MMX instructions requiring SSSE3.
@@ -163,12 +163,12 @@ multiclass SS3I_binop_rm_int_mm<bits<8>
Intrinsic IntId64, OpndItins itins,
bit Commutable = 0> {
let isCommutable = Commutable in
- def rr64 : MMXSS38I<opc, MRMSrcReg, (outs VR64:$dst),
+ def rr : MMXSS38I<opc, MRMSrcReg, (outs VR64:$dst),
(ins VR64:$src1, VR64:$src2),
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
[(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))], itins.rr>,
Sched<[itins.Sched]>;
- def rm64 : MMXSS38I<opc, MRMSrcMem, (outs VR64:$dst),
+ def rm : MMXSS38I<opc, MRMSrcMem, (outs VR64:$dst),
(ins VR64:$src1, i64mem:$src2),
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
[(set VR64:$dst,
@@ -180,12 +180,12 @@ multiclass SS3I_binop_rm_int_mm<bits<8>
/// PALIGN MMX instructions (require SSSE3).
multiclass ssse3_palign_mm<string asm, Intrinsic IntId> {
- def R64irr : MMXSS3AI<0x0F, MRMSrcReg, (outs VR64:$dst),
+ def rri : MMXSS3AI<0x0F, MRMSrcReg, (outs VR64:$dst),
(ins VR64:$src1, VR64:$src2, u8imm:$src3),
!strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
[(set VR64:$dst, (IntId VR64:$src1, VR64:$src2, (i8 imm:$src3)))]>,
Sched<[WriteShuffle]>;
- def R64irm : MMXSS3AI<0x0F, MRMSrcMem, (outs VR64:$dst),
+ def rmi : MMXSS3AI<0x0F, MRMSrcMem, (outs VR64:$dst),
(ins VR64:$src1, i64mem:$src2, u8imm:$src3),
!strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
[(set VR64:$dst, (IntId VR64:$src1,
@@ -470,7 +470,7 @@ defm MMX_PSIGNW : SS3I_binop_rm_int_mm<
defm MMX_PSIGND : SS3I_binop_rm_int_mm<0x0A, "psignd", int_x86_ssse3_psign_d,
MMX_MISC_FUNC_ITINS>;
let Constraints = "$src1 = $dst" in
- defm MMX_PALIGN : ssse3_palign_mm<"palignr", int_x86_mmx_palignr_b>;
+ defm MMX_PALIGNR : ssse3_palign_mm<"palignr", int_x86_mmx_palignr_b>;
// Logical Instructions
defm MMX_PAND : MMXI_binop_rm_int<0xDB, "pand", int_x86_mmx_pand,
Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=323402&r1=323401&r2=323402&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Wed Jan 24 20:45:30 2018
@@ -5101,14 +5101,14 @@ multiclass SS3I_binop_rm_int<bits<8> opc
Intrinsic IntId128, OpndItins itins,
PatFrag ld_frag, bit Is2Addr = 1> {
let isCommutable = 1 in
- def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
+ def rr : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
(ins VR128:$src1, VR128:$src2),
!if(Is2Addr,
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
[(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))], itins.rr>,
Sched<[itins.Sched]>;
- def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
+ def rm : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
(ins VR128:$src1, i128mem:$src2),
!if(Is2Addr,
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
@@ -5123,12 +5123,12 @@ multiclass SS3I_binop_rm_int_y<bits<8> o
Intrinsic IntId256,
X86FoldableSchedWrite Sched> {
let isCommutable = 1 in
- def rr256 : SS38I<opc, MRMSrcReg, (outs VR256:$dst),
+ def Yrr : SS38I<opc, MRMSrcReg, (outs VR256:$dst),
(ins VR256:$src1, VR256:$src2),
!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
[(set VR256:$dst, (IntId256 VR256:$src1, VR256:$src2))]>,
Sched<[Sched]>;
- def rm256 : SS38I<opc, MRMSrcMem, (outs VR256:$dst),
+ def Yrm : SS38I<opc, MRMSrcMem, (outs VR256:$dst),
(ins VR256:$src1, i256mem:$src2),
!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
[(set VR256:$dst,
@@ -5210,18 +5210,18 @@ let isCommutable = 0 in {
defm VPHSUBDY : SS3I_binop_rm<0x06, "vphsubd", X86hsub, v8i32, v8i32, VR256,
loadv4i64, i256mem,
SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
- defm VPSIGNBY : SS3I_binop_rm_int_y<0x08, "vpsignb", int_x86_avx2_psign_b,
- WriteVecALU>, VEX_4V, VEX_L, VEX_WIG;
- defm VPSIGNWY : SS3I_binop_rm_int_y<0x09, "vpsignw", int_x86_avx2_psign_w,
- WriteVecALU>, VEX_4V, VEX_L, VEX_WIG;
- defm VPSIGNDY : SS3I_binop_rm_int_y<0x0A, "vpsignd", int_x86_avx2_psign_d,
- WriteVecALU>, VEX_4V, VEX_L, VEX_WIG;
- defm VPHADDSW : SS3I_binop_rm_int_y<0x03, "vphaddsw",
- int_x86_avx2_phadd_sw,
- WriteVecALU>, VEX_4V, VEX_L, VEX_WIG;
- defm VPHSUBSW : SS3I_binop_rm_int_y<0x07, "vphsubsw",
- int_x86_avx2_phsub_sw,
- WriteVecALU>, VEX_4V, VEX_L, VEX_WIG;
+ defm VPSIGNB : SS3I_binop_rm_int_y<0x08, "vpsignb", int_x86_avx2_psign_b,
+ WriteVecALU>, VEX_4V, VEX_L, VEX_WIG;
+ defm VPSIGNW : SS3I_binop_rm_int_y<0x09, "vpsignw", int_x86_avx2_psign_w,
+ WriteVecALU>, VEX_4V, VEX_L, VEX_WIG;
+ defm VPSIGND : SS3I_binop_rm_int_y<0x0A, "vpsignd", int_x86_avx2_psign_d,
+ WriteVecALU>, VEX_4V, VEX_L, VEX_WIG;
+ defm VPHADDSW : SS3I_binop_rm_int_y<0x03, "vphaddsw",
+ int_x86_avx2_phadd_sw,
+ WriteVecALU>, VEX_4V, VEX_L, VEX_WIG;
+ defm VPHSUBSW : SS3I_binop_rm_int_y<0x07, "vphsubsw",
+ int_x86_avx2_phsub_sw,
+ WriteVecALU>, VEX_4V, VEX_L, VEX_WIG;
}
}
@@ -6276,17 +6276,17 @@ let Defs = [EFLAGS], Predicates = [HasPO
multiclass SS41I_unop_rm_int_v16<bits<8> opc, string OpcodeStr,
SDNode OpNode, PatFrag ld_frag,
X86FoldableSchedWrite Sched> {
- def rr128 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
- (ins VR128:$src),
- !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
- [(set VR128:$dst, (v8i16 (OpNode (v8i16 VR128:$src))))]>,
- Sched<[Sched]>;
- def rm128 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
- (ins i128mem:$src),
- !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
- [(set VR128:$dst,
- (v8i16 (OpNode (v8i16 (bitconvert (ld_frag addr:$src))))))]>,
- Sched<[Sched.Folded]>;
+ def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
+ (ins VR128:$src),
+ !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
+ [(set VR128:$dst, (v8i16 (OpNode (v8i16 VR128:$src))))]>,
+ Sched<[Sched]>;
+ def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
+ (ins i128mem:$src),
+ !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
+ [(set VR128:$dst,
+ (v8i16 (OpNode (v8i16 (bitconvert (ld_frag addr:$src))))))]>,
+ Sched<[Sched.Folded]>;
}
// PHMIN has the same profile as PSAD, thus we use the same scheduling
Modified: llvm/trunk/lib/Target/X86/X86SchedBroadwell.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedBroadwell.td?rev=323402&r1=323401&r2=323402&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedBroadwell.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedBroadwell.td Wed Jan 24 20:45:30 2018
@@ -396,8 +396,8 @@ def: InstRW<[BWWriteResGroup3], (instreg
def: InstRW<[BWWriteResGroup3], (instregex "MMX_MOVD64rr")>;
def: InstRW<[BWWriteResGroup3], (instregex "MMX_MOVD64to64rr")>;
def: InstRW<[BWWriteResGroup3], (instregex "MMX_MOVQ2DQrr")>;
-def: InstRW<[BWWriteResGroup3], (instregex "MMX_PALIGNR64irr")>;
-def: InstRW<[BWWriteResGroup3], (instregex "MMX_PSHUFBrr64")>;
+def: InstRW<[BWWriteResGroup3], (instregex "MMX_PALIGNRrri")>;
+def: InstRW<[BWWriteResGroup3], (instregex "MMX_PSHUFBrr")>;
def: InstRW<[BWWriteResGroup3], (instregex "MMX_PSHUFWri")>;
def: InstRW<[BWWriteResGroup3], (instregex "MMX_PUNPCKHBWirr")>;
def: InstRW<[BWWriteResGroup3], (instregex "MMX_PUNPCKHDQirr")>;
@@ -645,9 +645,9 @@ def: InstRW<[BWWriteResGroup7], (instreg
def: InstRW<[BWWriteResGroup7], (instregex "BLSR(32|64)rr")>;
def: InstRW<[BWWriteResGroup7], (instregex "BZHI(32|64)rr")>;
def: InstRW<[BWWriteResGroup7], (instregex "LEA(16|32|64)(_32)?r")>;
-def: InstRW<[BWWriteResGroup7], (instregex "MMX_PABSBrr64")>;
-def: InstRW<[BWWriteResGroup7], (instregex "MMX_PABSDrr64")>;
-def: InstRW<[BWWriteResGroup7], (instregex "MMX_PABSWrr64")>;
+def: InstRW<[BWWriteResGroup7], (instregex "MMX_PABSBrr")>;
+def: InstRW<[BWWriteResGroup7], (instregex "MMX_PABSDrr")>;
+def: InstRW<[BWWriteResGroup7], (instregex "MMX_PABSWrr")>;
def: InstRW<[BWWriteResGroup7], (instregex "MMX_PADDBirr")>;
def: InstRW<[BWWriteResGroup7], (instregex "MMX_PADDDirr")>;
def: InstRW<[BWWriteResGroup7], (instregex "MMX_PADDQirr")>;
@@ -668,9 +668,9 @@ def: InstRW<[BWWriteResGroup7], (instreg
def: InstRW<[BWWriteResGroup7], (instregex "MMX_PMAXUBirr")>;
def: InstRW<[BWWriteResGroup7], (instregex "MMX_PMINSWirr")>;
def: InstRW<[BWWriteResGroup7], (instregex "MMX_PMINUBirr")>;
-def: InstRW<[BWWriteResGroup7], (instregex "MMX_PSIGNBrr64")>;
-def: InstRW<[BWWriteResGroup7], (instregex "MMX_PSIGNDrr64")>;
-def: InstRW<[BWWriteResGroup7], (instregex "MMX_PSIGNWrr64")>;
+def: InstRW<[BWWriteResGroup7], (instregex "MMX_PSIGNBrr")>;
+def: InstRW<[BWWriteResGroup7], (instregex "MMX_PSIGNDrr")>;
+def: InstRW<[BWWriteResGroup7], (instregex "MMX_PSIGNWrr")>;
def: InstRW<[BWWriteResGroup7], (instregex "MMX_PSUBBirr")>;
def: InstRW<[BWWriteResGroup7], (instregex "MMX_PSUBDirr")>;
def: InstRW<[BWWriteResGroup7], (instregex "MMX_PSUBQirr")>;
@@ -711,9 +711,9 @@ def: InstRW<[BWWriteResGroup7], (instreg
def: InstRW<[BWWriteResGroup7], (instregex "PMINUBrr")>;
def: InstRW<[BWWriteResGroup7], (instregex "PMINUDrr")>;
def: InstRW<[BWWriteResGroup7], (instregex "PMINUWrr")>;
-def: InstRW<[BWWriteResGroup7], (instregex "PSIGNBrr128")>;
-def: InstRW<[BWWriteResGroup7], (instregex "PSIGNDrr128")>;
-def: InstRW<[BWWriteResGroup7], (instregex "PSIGNWrr128")>;
+def: InstRW<[BWWriteResGroup7], (instregex "PSIGNBrr")>;
+def: InstRW<[BWWriteResGroup7], (instregex "PSIGNDrr")>;
+def: InstRW<[BWWriteResGroup7], (instregex "PSIGNWrr")>;
def: InstRW<[BWWriteResGroup7], (instregex "PSUBBrr")>;
def: InstRW<[BWWriteResGroup7], (instregex "PSUBDrr")>;
def: InstRW<[BWWriteResGroup7], (instregex "PSUBQrr")>;
@@ -786,12 +786,12 @@ def: InstRW<[BWWriteResGroup7], (instreg
def: InstRW<[BWWriteResGroup7], (instregex "VPMINUDrr")>;
def: InstRW<[BWWriteResGroup7], (instregex "VPMINUWYrr")>;
def: InstRW<[BWWriteResGroup7], (instregex "VPMINUWrr")>;
-def: InstRW<[BWWriteResGroup7], (instregex "VPSIGNBYrr256")>;
-def: InstRW<[BWWriteResGroup7], (instregex "VPSIGNBrr128")>;
-def: InstRW<[BWWriteResGroup7], (instregex "VPSIGNDYrr256")>;
-def: InstRW<[BWWriteResGroup7], (instregex "VPSIGNDrr128")>;
-def: InstRW<[BWWriteResGroup7], (instregex "VPSIGNWYrr256")>;
-def: InstRW<[BWWriteResGroup7], (instregex "VPSIGNWrr128")>;
+def: InstRW<[BWWriteResGroup7], (instregex "VPSIGNBYrr")>;
+def: InstRW<[BWWriteResGroup7], (instregex "VPSIGNBrr")>;
+def: InstRW<[BWWriteResGroup7], (instregex "VPSIGNDYrr")>;
+def: InstRW<[BWWriteResGroup7], (instregex "VPSIGNDrr")>;
+def: InstRW<[BWWriteResGroup7], (instregex "VPSIGNWYrr")>;
+def: InstRW<[BWWriteResGroup7], (instregex "VPSIGNWrr")>;
def: InstRW<[BWWriteResGroup7], (instregex "VPSUBBYrr")>;
def: InstRW<[BWWriteResGroup7], (instregex "VPSUBBrr")>;
def: InstRW<[BWWriteResGroup7], (instregex "VPSUBDYrr")>;
@@ -1378,28 +1378,28 @@ def BWWriteResGroup32 : SchedWriteRes<[B
let NumMicroOps = 3;
let ResourceCycles = [2,1];
}
-def: InstRW<[BWWriteResGroup32], (instregex "MMX_PHADDSWrr64")>;
-def: InstRW<[BWWriteResGroup32], (instregex "MMX_PHADDWrr64")>;
-def: InstRW<[BWWriteResGroup32], (instregex "MMX_PHADDrr64")>;
-def: InstRW<[BWWriteResGroup32], (instregex "MMX_PHSUBDrr64")>;
-def: InstRW<[BWWriteResGroup32], (instregex "MMX_PHSUBSWrr64")>;
-def: InstRW<[BWWriteResGroup32], (instregex "MMX_PHSUBWrr64")>;
+def: InstRW<[BWWriteResGroup32], (instregex "MMX_PHADDSWrr")>;
+def: InstRW<[BWWriteResGroup32], (instregex "MMX_PHADDWrr")>;
+def: InstRW<[BWWriteResGroup32], (instregex "MMX_PHADDrr")>;
+def: InstRW<[BWWriteResGroup32], (instregex "MMX_PHSUBDrr")>;
+def: InstRW<[BWWriteResGroup32], (instregex "MMX_PHSUBSWrr")>;
+def: InstRW<[BWWriteResGroup32], (instregex "MMX_PHSUBWrr")>;
def: InstRW<[BWWriteResGroup32], (instregex "PHADDDrr")>;
-def: InstRW<[BWWriteResGroup32], (instregex "PHADDSWrr128")>;
+def: InstRW<[BWWriteResGroup32], (instregex "PHADDSWrr")>;
def: InstRW<[BWWriteResGroup32], (instregex "PHADDWrr")>;
def: InstRW<[BWWriteResGroup32], (instregex "PHSUBDrr")>;
-def: InstRW<[BWWriteResGroup32], (instregex "PHSUBSWrr128")>;
+def: InstRW<[BWWriteResGroup32], (instregex "PHSUBSWrr")>;
def: InstRW<[BWWriteResGroup32], (instregex "PHSUBWrr")>;
def: InstRW<[BWWriteResGroup32], (instregex "VPHADDDYrr")>;
def: InstRW<[BWWriteResGroup32], (instregex "VPHADDDrr")>;
-def: InstRW<[BWWriteResGroup32], (instregex "VPHADDSWrr128")>;
-def: InstRW<[BWWriteResGroup32], (instregex "VPHADDSWrr256")>;
+def: InstRW<[BWWriteResGroup32], (instregex "VPHADDSWYrr")>;
+def: InstRW<[BWWriteResGroup32], (instregex "VPHADDSWrr")>;
def: InstRW<[BWWriteResGroup32], (instregex "VPHADDWYrr")>;
def: InstRW<[BWWriteResGroup32], (instregex "VPHADDWrr")>;
def: InstRW<[BWWriteResGroup32], (instregex "VPHSUBDYrr")>;
def: InstRW<[BWWriteResGroup32], (instregex "VPHSUBDrr")>;
-def: InstRW<[BWWriteResGroup32], (instregex "VPHSUBSWrr128")>;
-def: InstRW<[BWWriteResGroup32], (instregex "VPHSUBSWrr256")>;
+def: InstRW<[BWWriteResGroup32], (instregex "VPHSUBSWYrr")>;
+def: InstRW<[BWWriteResGroup32], (instregex "VPHSUBSWrr")>;
def: InstRW<[BWWriteResGroup32], (instregex "VPHSUBWYrr")>;
def: InstRW<[BWWriteResGroup32], (instregex "VPHSUBWrr")>;
@@ -1589,9 +1589,9 @@ def BWWriteResGroup47 : SchedWriteRes<[B
let NumMicroOps = 1;
let ResourceCycles = [1];
}
-def: InstRW<[BWWriteResGroup47], (instregex "MMX_PMADDUBSWrr64")>;
+def: InstRW<[BWWriteResGroup47], (instregex "MMX_PMADDUBSWrr")>;
def: InstRW<[BWWriteResGroup47], (instregex "MMX_PMADDWDirr")>;
-def: InstRW<[BWWriteResGroup47], (instregex "MMX_PMULHRSWrr64")>;
+def: InstRW<[BWWriteResGroup47], (instregex "MMX_PMULHRSWrr")>;
def: InstRW<[BWWriteResGroup47], (instregex "MMX_PMULHUWirr")>;
def: InstRW<[BWWriteResGroup47], (instregex "MMX_PMULHWirr")>;
def: InstRW<[BWWriteResGroup47], (instregex "MMX_PMULLWirr")>;
@@ -1602,7 +1602,7 @@ def: InstRW<[BWWriteResGroup47], (instre
def: InstRW<[BWWriteResGroup47], (instregex "MUL_FrST0")>;
def: InstRW<[BWWriteResGroup47], (instregex "PCLMULQDQrr")>;
def: InstRW<[BWWriteResGroup47], (instregex "PCMPGTQrr")>;
-def: InstRW<[BWWriteResGroup47], (instregex "PHMINPOSUWrr128")>;
+def: InstRW<[BWWriteResGroup47], (instregex "PHMINPOSUWrr")>;
def: InstRW<[BWWriteResGroup47], (instregex "PMADDUBSWrr")>;
def: InstRW<[BWWriteResGroup47], (instregex "PMADDWDrr")>;
def: InstRW<[BWWriteResGroup47], (instregex "PMULDQrr")>;
@@ -1619,7 +1619,7 @@ def: InstRW<[BWWriteResGroup47], (instre
def: InstRW<[BWWriteResGroup47], (instregex "VPCLMULQDQrr")>;
def: InstRW<[BWWriteResGroup47], (instregex "VPCMPGTQYrr")>;
def: InstRW<[BWWriteResGroup47], (instregex "VPCMPGTQrr")>;
-def: InstRW<[BWWriteResGroup47], (instregex "VPHMINPOSUWrr128")>;
+def: InstRW<[BWWriteResGroup47], (instregex "VPHMINPOSUWrr")>;
def: InstRW<[BWWriteResGroup47], (instregex "VPMADDUBSWYrr")>;
def: InstRW<[BWWriteResGroup47], (instregex "VPMADDUBSWrr")>;
def: InstRW<[BWWriteResGroup47], (instregex "VPMADDWDYrr")>;
@@ -1867,9 +1867,9 @@ def: InstRW<[BWWriteResGroup61], (instre
def: InstRW<[BWWriteResGroup61], (instregex "ANDPDrm")>;
def: InstRW<[BWWriteResGroup61], (instregex "ANDPSrm")>;
def: InstRW<[BWWriteResGroup61], (instregex "INSERTPSrm")>;
-def: InstRW<[BWWriteResGroup61], (instregex "MMX_PALIGNR64irm")>;
+def: InstRW<[BWWriteResGroup61], (instregex "MMX_PALIGNRrmi")>;
def: InstRW<[BWWriteResGroup61], (instregex "MMX_PINSRWrm")>;
-def: InstRW<[BWWriteResGroup61], (instregex "MMX_PSHUFBrm64")>;
+def: InstRW<[BWWriteResGroup61], (instregex "MMX_PSHUFBrm")>;
def: InstRW<[BWWriteResGroup61], (instregex "MMX_PSHUFWmi")>;
def: InstRW<[BWWriteResGroup61], (instregex "MMX_PUNPCKHBWirm")>;
def: InstRW<[BWWriteResGroup61], (instregex "MMX_PUNPCKHDQirm")>;
@@ -2019,9 +2019,9 @@ def: InstRW<[BWWriteResGroup64], (instre
def: InstRW<[BWWriteResGroup64], (instregex "BLSMSK(32|64)rm")>;
def: InstRW<[BWWriteResGroup64], (instregex "BLSR(32|64)rm")>;
def: InstRW<[BWWriteResGroup64], (instregex "BZHI(32|64)rm")>;
-def: InstRW<[BWWriteResGroup64], (instregex "MMX_PABSBrm64")>;
-def: InstRW<[BWWriteResGroup64], (instregex "MMX_PABSDrm64")>;
-def: InstRW<[BWWriteResGroup64], (instregex "MMX_PABSWrm64")>;
+def: InstRW<[BWWriteResGroup64], (instregex "MMX_PABSBrm")>;
+def: InstRW<[BWWriteResGroup64], (instregex "MMX_PABSDrm")>;
+def: InstRW<[BWWriteResGroup64], (instregex "MMX_PABSWrm")>;
def: InstRW<[BWWriteResGroup64], (instregex "MMX_PADDBirm")>;
def: InstRW<[BWWriteResGroup64], (instregex "MMX_PADDDirm")>;
def: InstRW<[BWWriteResGroup64], (instregex "MMX_PADDQirm")>;
@@ -2042,9 +2042,9 @@ def: InstRW<[BWWriteResGroup64], (instre
def: InstRW<[BWWriteResGroup64], (instregex "MMX_PMAXUBirm")>;
def: InstRW<[BWWriteResGroup64], (instregex "MMX_PMINSWirm")>;
def: InstRW<[BWWriteResGroup64], (instregex "MMX_PMINUBirm")>;
-def: InstRW<[BWWriteResGroup64], (instregex "MMX_PSIGNBrm64")>;
-def: InstRW<[BWWriteResGroup64], (instregex "MMX_PSIGNDrm64")>;
-def: InstRW<[BWWriteResGroup64], (instregex "MMX_PSIGNWrm64")>;
+def: InstRW<[BWWriteResGroup64], (instregex "MMX_PSIGNBrm")>;
+def: InstRW<[BWWriteResGroup64], (instregex "MMX_PSIGNDrm")>;
+def: InstRW<[BWWriteResGroup64], (instregex "MMX_PSIGNWrm")>;
def: InstRW<[BWWriteResGroup64], (instregex "MMX_PSUBBirm")>;
def: InstRW<[BWWriteResGroup64], (instregex "MMX_PSUBDirm")>;
def: InstRW<[BWWriteResGroup64], (instregex "MMX_PSUBQirm")>;
@@ -2086,9 +2086,9 @@ def: InstRW<[BWWriteResGroup64], (instre
def: InstRW<[BWWriteResGroup64], (instregex "PMINUBrm")>;
def: InstRW<[BWWriteResGroup64], (instregex "PMINUDrm")>;
def: InstRW<[BWWriteResGroup64], (instregex "PMINUWrm")>;
-def: InstRW<[BWWriteResGroup64], (instregex "PSIGNBrm128")>;
-def: InstRW<[BWWriteResGroup64], (instregex "PSIGNDrm128")>;
-def: InstRW<[BWWriteResGroup64], (instregex "PSIGNWrm128")>;
+def: InstRW<[BWWriteResGroup64], (instregex "PSIGNBrm")>;
+def: InstRW<[BWWriteResGroup64], (instregex "PSIGNDrm")>;
+def: InstRW<[BWWriteResGroup64], (instregex "PSIGNWrm")>;
def: InstRW<[BWWriteResGroup64], (instregex "PSUBBrm")>;
def: InstRW<[BWWriteResGroup64], (instregex "PSUBDrm")>;
def: InstRW<[BWWriteResGroup64], (instregex "PSUBQrm")>;
@@ -2129,9 +2129,9 @@ def: InstRW<[BWWriteResGroup64], (instre
def: InstRW<[BWWriteResGroup64], (instregex "VPMINUBrm")>;
def: InstRW<[BWWriteResGroup64], (instregex "VPMINUDrm")>;
def: InstRW<[BWWriteResGroup64], (instregex "VPMINUWrm")>;
-def: InstRW<[BWWriteResGroup64], (instregex "VPSIGNBrm128")>;
-def: InstRW<[BWWriteResGroup64], (instregex "VPSIGNDrm128")>;
-def: InstRW<[BWWriteResGroup64], (instregex "VPSIGNWrm128")>;
+def: InstRW<[BWWriteResGroup64], (instregex "VPSIGNBrm")>;
+def: InstRW<[BWWriteResGroup64], (instregex "VPSIGNDrm")>;
+def: InstRW<[BWWriteResGroup64], (instregex "VPSIGNWrm")>;
def: InstRW<[BWWriteResGroup64], (instregex "VPSUBBrm")>;
def: InstRW<[BWWriteResGroup64], (instregex "VPSUBDrm")>;
def: InstRW<[BWWriteResGroup64], (instregex "VPSUBQrm")>;
@@ -2392,9 +2392,9 @@ def: InstRW<[BWWriteResGroup76], (instre
def: InstRW<[BWWriteResGroup76], (instregex "VPMINUBYrm")>;
def: InstRW<[BWWriteResGroup76], (instregex "VPMINUDYrm")>;
def: InstRW<[BWWriteResGroup76], (instregex "VPMINUWYrm")>;
-def: InstRW<[BWWriteResGroup76], (instregex "VPSIGNBYrm256")>;
-def: InstRW<[BWWriteResGroup76], (instregex "VPSIGNDYrm256")>;
-def: InstRW<[BWWriteResGroup76], (instregex "VPSIGNWYrm256")>;
+def: InstRW<[BWWriteResGroup76], (instregex "VPSIGNBYrm")>;
+def: InstRW<[BWWriteResGroup76], (instregex "VPSIGNDYrm")>;
+def: InstRW<[BWWriteResGroup76], (instregex "VPSIGNWYrm")>;
def: InstRW<[BWWriteResGroup76], (instregex "VPSUBBYrm")>;
def: InstRW<[BWWriteResGroup76], (instregex "VPSUBDYrm")>;
def: InstRW<[BWWriteResGroup76], (instregex "VPSUBQYrm")>;
@@ -2709,23 +2709,23 @@ def BWWriteResGroup96 : SchedWriteRes<[B
let NumMicroOps = 4;
let ResourceCycles = [2,1,1];
}
-def: InstRW<[BWWriteResGroup96], (instregex "MMX_PHADDSWrm64")>;
-def: InstRW<[BWWriteResGroup96], (instregex "MMX_PHADDWrm64")>;
-def: InstRW<[BWWriteResGroup96], (instregex "MMX_PHADDrm64")>;
-def: InstRW<[BWWriteResGroup96], (instregex "MMX_PHSUBDrm64")>;
-def: InstRW<[BWWriteResGroup96], (instregex "MMX_PHSUBSWrm64")>;
-def: InstRW<[BWWriteResGroup96], (instregex "MMX_PHSUBWrm64")>;
+def: InstRW<[BWWriteResGroup96], (instregex "MMX_PHADDSWrm")>;
+def: InstRW<[BWWriteResGroup96], (instregex "MMX_PHADDWrm")>;
+def: InstRW<[BWWriteResGroup96], (instregex "MMX_PHADDrm")>;
+def: InstRW<[BWWriteResGroup96], (instregex "MMX_PHSUBDrm")>;
+def: InstRW<[BWWriteResGroup96], (instregex "MMX_PHSUBSWrm")>;
+def: InstRW<[BWWriteResGroup96], (instregex "MMX_PHSUBWrm")>;
def: InstRW<[BWWriteResGroup96], (instregex "PHADDDrm")>;
-def: InstRW<[BWWriteResGroup96], (instregex "PHADDSWrm128")>;
+def: InstRW<[BWWriteResGroup96], (instregex "PHADDSWrm")>;
def: InstRW<[BWWriteResGroup96], (instregex "PHADDWrm")>;
def: InstRW<[BWWriteResGroup96], (instregex "PHSUBDrm")>;
-def: InstRW<[BWWriteResGroup96], (instregex "PHSUBSWrm128")>;
+def: InstRW<[BWWriteResGroup96], (instregex "PHSUBSWrm")>;
def: InstRW<[BWWriteResGroup96], (instregex "PHSUBWrm")>;
def: InstRW<[BWWriteResGroup96], (instregex "VPHADDDrm")>;
-def: InstRW<[BWWriteResGroup96], (instregex "VPHADDSWrm128")>;
+def: InstRW<[BWWriteResGroup96], (instregex "VPHADDSWrm")>;
def: InstRW<[BWWriteResGroup96], (instregex "VPHADDWrm")>;
def: InstRW<[BWWriteResGroup96], (instregex "VPHSUBDrm")>;
-def: InstRW<[BWWriteResGroup96], (instregex "VPHSUBSWrm128")>;
+def: InstRW<[BWWriteResGroup96], (instregex "VPHSUBSWrm")>;
def: InstRW<[BWWriteResGroup96], (instregex "VPHSUBWrm")>;
def BWWriteResGroup97 : SchedWriteRes<[BWPort23,BWPort237,BWPort06,BWPort0156]> {
@@ -2920,10 +2920,10 @@ def BWWriteResGroup110 : SchedWriteRes<[
let ResourceCycles = [2,1,1];
}
def: InstRW<[BWWriteResGroup110], (instregex "VPHADDDYrm")>;
-def: InstRW<[BWWriteResGroup110], (instregex "VPHADDSWrm256")>;
+def: InstRW<[BWWriteResGroup110], (instregex "VPHADDSWYrm")>;
def: InstRW<[BWWriteResGroup110], (instregex "VPHADDWYrm")>;
def: InstRW<[BWWriteResGroup110], (instregex "VPHSUBDYrm")>;
-def: InstRW<[BWWriteResGroup110], (instregex "VPHSUBSWrm256")>;
+def: InstRW<[BWWriteResGroup110], (instregex "VPHSUBSWYrm")>;
def: InstRW<[BWWriteResGroup110], (instregex "VPHSUBWYrm")>;
def BWWriteResGroup111 : SchedWriteRes<[BWPort1,BWPort23,BWPort237,BWPort0156]> {
@@ -2963,9 +2963,9 @@ def BWWriteResGroup115 : SchedWriteRes<[
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[BWWriteResGroup115], (instregex "MMX_PMADDUBSWrm64")>;
+def: InstRW<[BWWriteResGroup115], (instregex "MMX_PMADDUBSWrm")>;
def: InstRW<[BWWriteResGroup115], (instregex "MMX_PMADDWDirm")>;
-def: InstRW<[BWWriteResGroup115], (instregex "MMX_PMULHRSWrm64")>;
+def: InstRW<[BWWriteResGroup115], (instregex "MMX_PMULHRSWrm")>;
def: InstRW<[BWWriteResGroup115], (instregex "MMX_PMULHUWirm")>;
def: InstRW<[BWWriteResGroup115], (instregex "MMX_PMULHWirm")>;
def: InstRW<[BWWriteResGroup115], (instregex "MMX_PMULLWirm")>;
@@ -2973,7 +2973,7 @@ def: InstRW<[BWWriteResGroup115], (instr
def: InstRW<[BWWriteResGroup115], (instregex "MMX_PSADBWirm")>;
def: InstRW<[BWWriteResGroup115], (instregex "PCLMULQDQrm")>;
def: InstRW<[BWWriteResGroup115], (instregex "PCMPGTQrm")>;
-def: InstRW<[BWWriteResGroup115], (instregex "PHMINPOSUWrm128")>;
+def: InstRW<[BWWriteResGroup115], (instregex "PHMINPOSUWrm")>;
def: InstRW<[BWWriteResGroup115], (instregex "PMADDUBSWrm")>;
def: InstRW<[BWWriteResGroup115], (instregex "PMADDWDrm")>;
def: InstRW<[BWWriteResGroup115], (instregex "PMULDQrm")>;
@@ -2989,7 +2989,7 @@ def: InstRW<[BWWriteResGroup115], (instr
def: InstRW<[BWWriteResGroup115], (instregex "RSQRTSSm")>;
def: InstRW<[BWWriteResGroup115], (instregex "VPCLMULQDQrm")>;
def: InstRW<[BWWriteResGroup115], (instregex "VPCMPGTQrm")>;
-def: InstRW<[BWWriteResGroup115], (instregex "VPHMINPOSUWrm128")>;
+def: InstRW<[BWWriteResGroup115], (instregex "VPHMINPOSUWrm")>;
def: InstRW<[BWWriteResGroup115], (instregex "VPMADDUBSWrm")>;
def: InstRW<[BWWriteResGroup115], (instregex "VPMADDWDrm")>;
def: InstRW<[BWWriteResGroup115], (instregex "VPMULDQrm")>;
Modified: llvm/trunk/lib/Target/X86/X86SchedHaswell.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedHaswell.td?rev=323402&r1=323401&r2=323402&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedHaswell.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedHaswell.td Wed Jan 24 20:45:30 2018
@@ -964,8 +964,8 @@ def: InstRW<[HWWriteResGroup4], (instreg
def: InstRW<[HWWriteResGroup4], (instregex "MMX_MOVD64rr")>;
def: InstRW<[HWWriteResGroup4], (instregex "MMX_MOVD64to64rr")>;
def: InstRW<[HWWriteResGroup4], (instregex "MMX_MOVQ2DQrr")>;
-def: InstRW<[HWWriteResGroup4], (instregex "MMX_PALIGNR64irr")>;
-def: InstRW<[HWWriteResGroup4], (instregex "MMX_PSHUFBrr64")>;
+def: InstRW<[HWWriteResGroup4], (instregex "MMX_PALIGNRrri")>;
+def: InstRW<[HWWriteResGroup4], (instregex "MMX_PSHUFBrr")>;
def: InstRW<[HWWriteResGroup4], (instregex "MMX_PSHUFWri")>;
def: InstRW<[HWWriteResGroup4], (instregex "MMX_PUNPCKHBWirr")>;
def: InstRW<[HWWriteResGroup4], (instregex "MMX_PUNPCKHDQirr")>;
@@ -1204,9 +1204,9 @@ def: InstRW<[HWWriteResGroup8], (instreg
def: InstRW<[HWWriteResGroup8], (instregex "BLSR(32|64)rr")>;
def: InstRW<[HWWriteResGroup8], (instregex "BZHI(32|64)rr")>;
def: InstRW<[HWWriteResGroup8], (instregex "LEA(16|32|64)(_32)?r")>;
-def: InstRW<[HWWriteResGroup8], (instregex "MMX_PABSBrr64")>;
-def: InstRW<[HWWriteResGroup8], (instregex "MMX_PABSDrr64")>;
-def: InstRW<[HWWriteResGroup8], (instregex "MMX_PABSWrr64")>;
+def: InstRW<[HWWriteResGroup8], (instregex "MMX_PABSBrr")>;
+def: InstRW<[HWWriteResGroup8], (instregex "MMX_PABSDrr")>;
+def: InstRW<[HWWriteResGroup8], (instregex "MMX_PABSWrr")>;
def: InstRW<[HWWriteResGroup8], (instregex "MMX_PADDBirr")>;
def: InstRW<[HWWriteResGroup8], (instregex "MMX_PADDDirr")>;
def: InstRW<[HWWriteResGroup8], (instregex "MMX_PADDQirr")>;
@@ -1227,9 +1227,9 @@ def: InstRW<[HWWriteResGroup8], (instreg
def: InstRW<[HWWriteResGroup8], (instregex "MMX_PMAXUBirr")>;
def: InstRW<[HWWriteResGroup8], (instregex "MMX_PMINSWirr")>;
def: InstRW<[HWWriteResGroup8], (instregex "MMX_PMINUBirr")>;
-def: InstRW<[HWWriteResGroup8], (instregex "MMX_PSIGNBrr64")>;
-def: InstRW<[HWWriteResGroup8], (instregex "MMX_PSIGNDrr64")>;
-def: InstRW<[HWWriteResGroup8], (instregex "MMX_PSIGNWrr64")>;
+def: InstRW<[HWWriteResGroup8], (instregex "MMX_PSIGNBrr")>;
+def: InstRW<[HWWriteResGroup8], (instregex "MMX_PSIGNDrr")>;
+def: InstRW<[HWWriteResGroup8], (instregex "MMX_PSIGNWrr")>;
def: InstRW<[HWWriteResGroup8], (instregex "MMX_PSUBBirr")>;
def: InstRW<[HWWriteResGroup8], (instregex "MMX_PSUBDirr")>;
def: InstRW<[HWWriteResGroup8], (instregex "MMX_PSUBQirr")>;
@@ -1270,9 +1270,9 @@ def: InstRW<[HWWriteResGroup8], (instreg
def: InstRW<[HWWriteResGroup8], (instregex "PMINUBrr")>;
def: InstRW<[HWWriteResGroup8], (instregex "PMINUDrr")>;
def: InstRW<[HWWriteResGroup8], (instregex "PMINUWrr")>;
-def: InstRW<[HWWriteResGroup8], (instregex "PSIGNBrr128")>;
-def: InstRW<[HWWriteResGroup8], (instregex "PSIGNDrr128")>;
-def: InstRW<[HWWriteResGroup8], (instregex "PSIGNWrr128")>;
+def: InstRW<[HWWriteResGroup8], (instregex "PSIGNBrr")>;
+def: InstRW<[HWWriteResGroup8], (instregex "PSIGNDrr")>;
+def: InstRW<[HWWriteResGroup8], (instregex "PSIGNWrr")>;
def: InstRW<[HWWriteResGroup8], (instregex "PSUBBrr")>;
def: InstRW<[HWWriteResGroup8], (instregex "PSUBDrr")>;
def: InstRW<[HWWriteResGroup8], (instregex "PSUBQrr")>;
@@ -1345,12 +1345,12 @@ def: InstRW<[HWWriteResGroup8], (instreg
def: InstRW<[HWWriteResGroup8], (instregex "VPMINUDrr")>;
def: InstRW<[HWWriteResGroup8], (instregex "VPMINUWYrr")>;
def: InstRW<[HWWriteResGroup8], (instregex "VPMINUWrr")>;
-def: InstRW<[HWWriteResGroup8], (instregex "VPSIGNBYrr256")>;
-def: InstRW<[HWWriteResGroup8], (instregex "VPSIGNBrr128")>;
-def: InstRW<[HWWriteResGroup8], (instregex "VPSIGNDYrr256")>;
-def: InstRW<[HWWriteResGroup8], (instregex "VPSIGNDrr128")>;
-def: InstRW<[HWWriteResGroup8], (instregex "VPSIGNWYrr256")>;
-def: InstRW<[HWWriteResGroup8], (instregex "VPSIGNWrr128")>;
+def: InstRW<[HWWriteResGroup8], (instregex "VPSIGNBYrr")>;
+def: InstRW<[HWWriteResGroup8], (instregex "VPSIGNBrr")>;
+def: InstRW<[HWWriteResGroup8], (instregex "VPSIGNDYrr")>;
+def: InstRW<[HWWriteResGroup8], (instregex "VPSIGNDrr")>;
+def: InstRW<[HWWriteResGroup8], (instregex "VPSIGNWYrr")>;
+def: InstRW<[HWWriteResGroup8], (instregex "VPSIGNWrr")>;
def: InstRW<[HWWriteResGroup8], (instregex "VPSUBBYrr")>;
def: InstRW<[HWWriteResGroup8], (instregex "VPSUBBrr")>;
def: InstRW<[HWWriteResGroup8], (instregex "VPSUBDYrr")>;
@@ -1707,9 +1707,9 @@ def HWWriteResGroup13_2 : SchedWriteRes<
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[HWWriteResGroup13_2], (instregex "MMX_PALIGNR64irm")>;
+def: InstRW<[HWWriteResGroup13_2], (instregex "MMX_PALIGNRrmi")>;
def: InstRW<[HWWriteResGroup13_2], (instregex "MMX_PINSRWrm")>;
-def: InstRW<[HWWriteResGroup13_2], (instregex "MMX_PSHUFBrm64")>;
+def: InstRW<[HWWriteResGroup13_2], (instregex "MMX_PSHUFBrm")>;
def: InstRW<[HWWriteResGroup13_2], (instregex "MMX_PSHUFWmi")>;
def: InstRW<[HWWriteResGroup13_2], (instregex "MMX_PUNPCKHBWirm")>;
def: InstRW<[HWWriteResGroup13_2], (instregex "MMX_PUNPCKHDQirm")>;
@@ -1791,9 +1791,9 @@ def: InstRW<[HWWriteResGroup16], (instre
def: InstRW<[HWWriteResGroup16], (instregex "BLSMSK(32|64)rm")>;
def: InstRW<[HWWriteResGroup16], (instregex "BLSR(32|64)rm")>;
def: InstRW<[HWWriteResGroup16], (instregex "BZHI(32|64)rm")>;
-def: InstRW<[HWWriteResGroup16], (instregex "MMX_PABSBrm64")>;
-def: InstRW<[HWWriteResGroup16], (instregex "MMX_PABSDrm64")>;
-def: InstRW<[HWWriteResGroup16], (instregex "MMX_PABSWrm64")>;
+def: InstRW<[HWWriteResGroup16], (instregex "MMX_PABSBrm")>;
+def: InstRW<[HWWriteResGroup16], (instregex "MMX_PABSDrm")>;
+def: InstRW<[HWWriteResGroup16], (instregex "MMX_PABSWrm")>;
def: InstRW<[HWWriteResGroup16], (instregex "MMX_PADDBirm")>;
def: InstRW<[HWWriteResGroup16], (instregex "MMX_PADDDirm")>;
def: InstRW<[HWWriteResGroup16], (instregex "MMX_PADDQirm")>;
@@ -1814,9 +1814,9 @@ def: InstRW<[HWWriteResGroup16], (instre
def: InstRW<[HWWriteResGroup16], (instregex "MMX_PMAXUBirm")>;
def: InstRW<[HWWriteResGroup16], (instregex "MMX_PMINSWirm")>;
def: InstRW<[HWWriteResGroup16], (instregex "MMX_PMINUBirm")>;
-def: InstRW<[HWWriteResGroup16], (instregex "MMX_PSIGNBrm64")>;
-def: InstRW<[HWWriteResGroup16], (instregex "MMX_PSIGNDrm64")>;
-def: InstRW<[HWWriteResGroup16], (instregex "MMX_PSIGNWrm64")>;
+def: InstRW<[HWWriteResGroup16], (instregex "MMX_PSIGNBrm")>;
+def: InstRW<[HWWriteResGroup16], (instregex "MMX_PSIGNDrm")>;
+def: InstRW<[HWWriteResGroup16], (instregex "MMX_PSIGNWrm")>;
def: InstRW<[HWWriteResGroup16], (instregex "MMX_PSUBBirm")>;
def: InstRW<[HWWriteResGroup16], (instregex "MMX_PSUBDirm")>;
def: InstRW<[HWWriteResGroup16], (instregex "MMX_PSUBQirm")>;
@@ -1864,9 +1864,9 @@ def: InstRW<[HWWriteResGroup16_1], (inst
def: InstRW<[HWWriteResGroup16_1], (instregex "PMINUBrm")>;
def: InstRW<[HWWriteResGroup16_1], (instregex "PMINUDrm")>;
def: InstRW<[HWWriteResGroup16_1], (instregex "PMINUWrm")>;
-def: InstRW<[HWWriteResGroup16_1], (instregex "PSIGNBrm128")>;
-def: InstRW<[HWWriteResGroup16_1], (instregex "PSIGNDrm128")>;
-def: InstRW<[HWWriteResGroup16_1], (instregex "PSIGNWrm128")>;
+def: InstRW<[HWWriteResGroup16_1], (instregex "PSIGNBrm")>;
+def: InstRW<[HWWriteResGroup16_1], (instregex "PSIGNDrm")>;
+def: InstRW<[HWWriteResGroup16_1], (instregex "PSIGNWrm")>;
def: InstRW<[HWWriteResGroup16_1], (instregex "PSUBBrm")>;
def: InstRW<[HWWriteResGroup16_1], (instregex "PSUBDrm")>;
def: InstRW<[HWWriteResGroup16_1], (instregex "PSUBQrm")>;
@@ -1907,9 +1907,9 @@ def: InstRW<[HWWriteResGroup16_1], (inst
def: InstRW<[HWWriteResGroup16_1], (instregex "VPMINUBrm")>;
def: InstRW<[HWWriteResGroup16_1], (instregex "VPMINUDrm")>;
def: InstRW<[HWWriteResGroup16_1], (instregex "VPMINUWrm")>;
-def: InstRW<[HWWriteResGroup16_1], (instregex "VPSIGNBrm128")>;
-def: InstRW<[HWWriteResGroup16_1], (instregex "VPSIGNDrm128")>;
-def: InstRW<[HWWriteResGroup16_1], (instregex "VPSIGNWrm128")>;
+def: InstRW<[HWWriteResGroup16_1], (instregex "VPSIGNBrm")>;
+def: InstRW<[HWWriteResGroup16_1], (instregex "VPSIGNDrm")>;
+def: InstRW<[HWWriteResGroup16_1], (instregex "VPSIGNWrm")>;
def: InstRW<[HWWriteResGroup16_1], (instregex "VPSUBBrm")>;
def: InstRW<[HWWriteResGroup16_1], (instregex "VPSUBDrm")>;
def: InstRW<[HWWriteResGroup16_1], (instregex "VPSUBQrm")>;
@@ -1956,9 +1956,9 @@ def: InstRW<[HWWriteResGroup16_2], (inst
def: InstRW<[HWWriteResGroup16_2], (instregex "VPMINUBYrm")>;
def: InstRW<[HWWriteResGroup16_2], (instregex "VPMINUDYrm")>;
def: InstRW<[HWWriteResGroup16_2], (instregex "VPMINUWYrm")>;
-def: InstRW<[HWWriteResGroup16_2], (instregex "VPSIGNBYrm256")>;
-def: InstRW<[HWWriteResGroup16_2], (instregex "VPSIGNDYrm256")>;
-def: InstRW<[HWWriteResGroup16_2], (instregex "VPSIGNWYrm256")>;
+def: InstRW<[HWWriteResGroup16_2], (instregex "VPSIGNBYrm")>;
+def: InstRW<[HWWriteResGroup16_2], (instregex "VPSIGNDYrm")>;
+def: InstRW<[HWWriteResGroup16_2], (instregex "VPSIGNWYrm")>;
def: InstRW<[HWWriteResGroup16_2], (instregex "VPSUBBYrm")>;
def: InstRW<[HWWriteResGroup16_2], (instregex "VPSUBDYrm")>;
def: InstRW<[HWWriteResGroup16_2], (instregex "VPSUBQYrm")>;
@@ -2741,28 +2741,28 @@ def HWWriteResGroup56 : SchedWriteRes<[H
let NumMicroOps = 3;
let ResourceCycles = [2,1];
}
-def: InstRW<[HWWriteResGroup56], (instregex "MMX_PHADDSWrr64")>;
-def: InstRW<[HWWriteResGroup56], (instregex "MMX_PHADDWrr64")>;
-def: InstRW<[HWWriteResGroup56], (instregex "MMX_PHADDrr64")>;
-def: InstRW<[HWWriteResGroup56], (instregex "MMX_PHSUBDrr64")>;
-def: InstRW<[HWWriteResGroup56], (instregex "MMX_PHSUBSWrr64")>;
-def: InstRW<[HWWriteResGroup56], (instregex "MMX_PHSUBWrr64")>;
+def: InstRW<[HWWriteResGroup56], (instregex "MMX_PHADDSWrr")>;
+def: InstRW<[HWWriteResGroup56], (instregex "MMX_PHADDWrr")>;
+def: InstRW<[HWWriteResGroup56], (instregex "MMX_PHADDrr")>;
+def: InstRW<[HWWriteResGroup56], (instregex "MMX_PHSUBDrr")>;
+def: InstRW<[HWWriteResGroup56], (instregex "MMX_PHSUBSWrr")>;
+def: InstRW<[HWWriteResGroup56], (instregex "MMX_PHSUBWrr")>;
def: InstRW<[HWWriteResGroup56], (instregex "PHADDDrr")>;
-def: InstRW<[HWWriteResGroup56], (instregex "PHADDSWrr128")>;
+def: InstRW<[HWWriteResGroup56], (instregex "PHADDSWrr")>;
def: InstRW<[HWWriteResGroup56], (instregex "PHADDWrr")>;
def: InstRW<[HWWriteResGroup56], (instregex "PHSUBDrr")>;
-def: InstRW<[HWWriteResGroup56], (instregex "PHSUBSWrr128")>;
+def: InstRW<[HWWriteResGroup56], (instregex "PHSUBSWrr")>;
def: InstRW<[HWWriteResGroup56], (instregex "PHSUBWrr")>;
def: InstRW<[HWWriteResGroup56], (instregex "VPHADDDYrr")>;
def: InstRW<[HWWriteResGroup56], (instregex "VPHADDDrr")>;
-def: InstRW<[HWWriteResGroup56], (instregex "VPHADDSWrr128")>;
-def: InstRW<[HWWriteResGroup56], (instregex "VPHADDSWrr256")>;
+def: InstRW<[HWWriteResGroup56], (instregex "VPHADDSWrr")>;
+def: InstRW<[HWWriteResGroup56], (instregex "VPHADDSWYrr")>;
def: InstRW<[HWWriteResGroup56], (instregex "VPHADDWYrr")>;
def: InstRW<[HWWriteResGroup56], (instregex "VPHADDWrr")>;
def: InstRW<[HWWriteResGroup56], (instregex "VPHSUBDYrr")>;
def: InstRW<[HWWriteResGroup56], (instregex "VPHSUBDrr")>;
-def: InstRW<[HWWriteResGroup56], (instregex "VPHSUBSWrr128")>;
-def: InstRW<[HWWriteResGroup56], (instregex "VPHSUBSWrr256")>;
+def: InstRW<[HWWriteResGroup56], (instregex "VPHSUBSWrr")>;
+def: InstRW<[HWWriteResGroup56], (instregex "VPHSUBSWYrr")>;
def: InstRW<[HWWriteResGroup56], (instregex "VPHSUBWYrr")>;
def: InstRW<[HWWriteResGroup56], (instregex "VPHSUBWrr")>;
@@ -2857,12 +2857,12 @@ def HWWriteResGroup64 : SchedWriteRes<[H
let NumMicroOps = 4;
let ResourceCycles = [2,1,1];
}
-def: InstRW<[HWWriteResGroup64], (instregex "MMX_PHADDSWrm64")>;
-def: InstRW<[HWWriteResGroup64], (instregex "MMX_PHADDWrm64")>;
-def: InstRW<[HWWriteResGroup64], (instregex "MMX_PHADDrm64")>;
-def: InstRW<[HWWriteResGroup64], (instregex "MMX_PHSUBDrm64")>;
-def: InstRW<[HWWriteResGroup64], (instregex "MMX_PHSUBSWrm64")>;
-def: InstRW<[HWWriteResGroup64], (instregex "MMX_PHSUBWrm64")>;
+def: InstRW<[HWWriteResGroup64], (instregex "MMX_PHADDSWrm")>;
+def: InstRW<[HWWriteResGroup64], (instregex "MMX_PHADDWrm")>;
+def: InstRW<[HWWriteResGroup64], (instregex "MMX_PHADDrm")>;
+def: InstRW<[HWWriteResGroup64], (instregex "MMX_PHSUBDrm")>;
+def: InstRW<[HWWriteResGroup64], (instregex "MMX_PHSUBSWrm")>;
+def: InstRW<[HWWriteResGroup64], (instregex "MMX_PHSUBWrm")>;
def HWWriteResGroup64_1 : SchedWriteRes<[HWPort5,HWPort23,HWPort15]> {
let Latency = 10;
@@ -2870,10 +2870,10 @@ def HWWriteResGroup64_1 : SchedWriteRes<
let ResourceCycles = [2,1,1];
}
def: InstRW<[HWWriteResGroup64_1], (instregex "VPHADDDYrm")>;
-def: InstRW<[HWWriteResGroup64_1], (instregex "VPHADDSWrm256")>;
+def: InstRW<[HWWriteResGroup64_1], (instregex "VPHADDSWYrm")>;
def: InstRW<[HWWriteResGroup64_1], (instregex "VPHADDWYrm")>;
def: InstRW<[HWWriteResGroup64_1], (instregex "VPHSUBDYrm")>;
-def: InstRW<[HWWriteResGroup64_1], (instregex "VPHSUBSWrm256")>;
+def: InstRW<[HWWriteResGroup64_1], (instregex "VPHSUBSWYrm")>;
def: InstRW<[HWWriteResGroup64_1], (instregex "VPHSUBWYrm")>;
def HWWriteResGroup64_2 : SchedWriteRes<[HWPort5,HWPort23,HWPort15]> {
@@ -2882,16 +2882,16 @@ def HWWriteResGroup64_2 : SchedWriteRes<
let ResourceCycles = [2,1,1];
}
def: InstRW<[HWWriteResGroup64_2], (instregex "PHADDDrm")>;
-def: InstRW<[HWWriteResGroup64_2], (instregex "PHADDSWrm128")>;
+def: InstRW<[HWWriteResGroup64_2], (instregex "PHADDSWrm")>;
def: InstRW<[HWWriteResGroup64_2], (instregex "PHADDWrm")>;
def: InstRW<[HWWriteResGroup64_2], (instregex "PHSUBDrm")>;
-def: InstRW<[HWWriteResGroup64_2], (instregex "PHSUBSWrm128")>;
+def: InstRW<[HWWriteResGroup64_2], (instregex "PHSUBSWrm")>;
def: InstRW<[HWWriteResGroup64_2], (instregex "PHSUBWrm")>;
def: InstRW<[HWWriteResGroup64_2], (instregex "VPHADDDrm")>;
-def: InstRW<[HWWriteResGroup64_2], (instregex "VPHADDSWrm128")>;
+def: InstRW<[HWWriteResGroup64_2], (instregex "VPHADDSWrm")>;
def: InstRW<[HWWriteResGroup64_2], (instregex "VPHADDWrm")>;
def: InstRW<[HWWriteResGroup64_2], (instregex "VPHSUBDrm")>;
-def: InstRW<[HWWriteResGroup64_2], (instregex "VPHSUBSWrm128")>;
+def: InstRW<[HWWriteResGroup64_2], (instregex "VPHSUBSWrm")>;
def: InstRW<[HWWriteResGroup64_2], (instregex "VPHSUBWrm")>;
def HWWriteResGroup65 : SchedWriteRes<[HWPort23,HWPort06,HWPort0156]> {
@@ -3211,9 +3211,9 @@ def HWWriteResGroup89 : SchedWriteRes<[H
let NumMicroOps = 1;
let ResourceCycles = [1];
}
-def: InstRW<[HWWriteResGroup89], (instregex "MMX_PMADDUBSWrr64")>;
+def: InstRW<[HWWriteResGroup89], (instregex "MMX_PMADDUBSWrr")>;
def: InstRW<[HWWriteResGroup89], (instregex "MMX_PMADDWDirr")>;
-def: InstRW<[HWWriteResGroup89], (instregex "MMX_PMULHRSWrr64")>;
+def: InstRW<[HWWriteResGroup89], (instregex "MMX_PMULHRSWrr")>;
def: InstRW<[HWWriteResGroup89], (instregex "MMX_PMULHUWirr")>;
def: InstRW<[HWWriteResGroup89], (instregex "MMX_PMULHWirr")>;
def: InstRW<[HWWriteResGroup89], (instregex "MMX_PMULLWirr")>;
@@ -3223,7 +3223,7 @@ def: InstRW<[HWWriteResGroup89], (instre
def: InstRW<[HWWriteResGroup89], (instregex "MUL_FST0r")>;
def: InstRW<[HWWriteResGroup89], (instregex "MUL_FrST0")>;
def: InstRW<[HWWriteResGroup89], (instregex "PCMPGTQrr")>;
-def: InstRW<[HWWriteResGroup89], (instregex "PHMINPOSUWrr128")>;
+def: InstRW<[HWWriteResGroup89], (instregex "PHMINPOSUWrr")>;
def: InstRW<[HWWriteResGroup89], (instregex "PMADDUBSWrr")>;
def: InstRW<[HWWriteResGroup89], (instregex "PMADDWDrr")>;
def: InstRW<[HWWriteResGroup89], (instregex "PMULDQrr")>;
@@ -3239,7 +3239,7 @@ def: InstRW<[HWWriteResGroup89], (instre
def: InstRW<[HWWriteResGroup89], (instregex "RSQRTSSr")>;
def: InstRW<[HWWriteResGroup89], (instregex "VPCMPGTQYrr")>;
def: InstRW<[HWWriteResGroup89], (instregex "VPCMPGTQrr")>;
-def: InstRW<[HWWriteResGroup89], (instregex "VPHMINPOSUWrr128")>;
+def: InstRW<[HWWriteResGroup89], (instregex "VPHMINPOSUWrr")>;
def: InstRW<[HWWriteResGroup89], (instregex "VPMADDUBSWYrr")>;
def: InstRW<[HWWriteResGroup89], (instregex "VPMADDUBSWrr")>;
def: InstRW<[HWWriteResGroup89], (instregex "VPMADDWDYrr")>;
@@ -3287,9 +3287,9 @@ def HWWriteResGroup91 : SchedWriteRes<[H
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[HWWriteResGroup91], (instregex "MMX_PMADDUBSWrm64")>;
+def: InstRW<[HWWriteResGroup91], (instregex "MMX_PMADDUBSWrm")>;
def: InstRW<[HWWriteResGroup91], (instregex "MMX_PMADDWDirm")>;
-def: InstRW<[HWWriteResGroup91], (instregex "MMX_PMULHRSWrm64")>;
+def: InstRW<[HWWriteResGroup91], (instregex "MMX_PMULHRSWrm")>;
def: InstRW<[HWWriteResGroup91], (instregex "MMX_PMULHUWirm")>;
def: InstRW<[HWWriteResGroup91], (instregex "MMX_PMULHWirm")>;
def: InstRW<[HWWriteResGroup91], (instregex "MMX_PMULLWirm")>;
@@ -3314,7 +3314,7 @@ def HWWriteResGroup91_2 : SchedWriteRes<
let ResourceCycles = [1,1];
}
def: InstRW<[HWWriteResGroup91_2], (instregex "PCMPGTQrm")>;
-def: InstRW<[HWWriteResGroup91_2], (instregex "PHMINPOSUWrm128")>;
+def: InstRW<[HWWriteResGroup91_2], (instregex "PHMINPOSUWrm")>;
def: InstRW<[HWWriteResGroup91_2], (instregex "PMADDUBSWrm")>;
def: InstRW<[HWWriteResGroup91_2], (instregex "PMADDWDrm")>;
def: InstRW<[HWWriteResGroup91_2], (instregex "PMULDQrm")>;
@@ -3327,7 +3327,7 @@ def: InstRW<[HWWriteResGroup91_2], (inst
def: InstRW<[HWWriteResGroup91_2], (instregex "RCPPSm")>;
def: InstRW<[HWWriteResGroup91_2], (instregex "RSQRTPSm")>;
def: InstRW<[HWWriteResGroup91_2], (instregex "VPCMPGTQrm")>;
-def: InstRW<[HWWriteResGroup91_2], (instregex "VPHMINPOSUWrm128")>;
+def: InstRW<[HWWriteResGroup91_2], (instregex "VPHMINPOSUWrm")>;
def: InstRW<[HWWriteResGroup91_2], (instregex "VPMADDUBSWrm")>;
def: InstRW<[HWWriteResGroup91_2], (instregex "VPMADDWDrm")>;
def: InstRW<[HWWriteResGroup91_2], (instregex "VPMULDQrm")>;
Modified: llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td?rev=323402&r1=323401&r2=323402&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td Wed Jan 24 20:45:30 2018
@@ -483,15 +483,15 @@ def SBWriteResGroup5 : SchedWriteRes<[SB
let NumMicroOps = 1;
let ResourceCycles = [1];
}
-def: InstRW<[SBWriteResGroup5], (instregex "MMX_PABSBrr64")>;
-def: InstRW<[SBWriteResGroup5], (instregex "MMX_PABSDrr64")>;
-def: InstRW<[SBWriteResGroup5], (instregex "MMX_PABSWrr64")>;
+def: InstRW<[SBWriteResGroup5], (instregex "MMX_PABSBrr")>;
+def: InstRW<[SBWriteResGroup5], (instregex "MMX_PABSDrr")>;
+def: InstRW<[SBWriteResGroup5], (instregex "MMX_PABSWrr")>;
def: InstRW<[SBWriteResGroup5], (instregex "MMX_PADDQirr")>;
-def: InstRW<[SBWriteResGroup5], (instregex "MMX_PALIGNR64irr")>;
-def: InstRW<[SBWriteResGroup5], (instregex "MMX_PSHUFBrr64")>;
-def: InstRW<[SBWriteResGroup5], (instregex "MMX_PSIGNBrr64")>;
-def: InstRW<[SBWriteResGroup5], (instregex "MMX_PSIGNDrr64")>;
-def: InstRW<[SBWriteResGroup5], (instregex "MMX_PSIGNWrr64")>;
+def: InstRW<[SBWriteResGroup5], (instregex "MMX_PALIGNRrri")>;
+def: InstRW<[SBWriteResGroup5], (instregex "MMX_PSHUFBrr")>;
+def: InstRW<[SBWriteResGroup5], (instregex "MMX_PSIGNBrr")>;
+def: InstRW<[SBWriteResGroup5], (instregex "MMX_PSIGNDrr")>;
+def: InstRW<[SBWriteResGroup5], (instregex "MMX_PSIGNWrr")>;
def: InstRW<[SBWriteResGroup5], (instregex "PABSBrr")>;
def: InstRW<[SBWriteResGroup5], (instregex "PABSDrr")>;
def: InstRW<[SBWriteResGroup5], (instregex "PABSWrr")>;
@@ -546,9 +546,9 @@ def: InstRW<[SBWriteResGroup5], (instreg
def: InstRW<[SBWriteResGroup5], (instregex "PSHUFDri")>;
def: InstRW<[SBWriteResGroup5], (instregex "PSHUFHWri")>;
def: InstRW<[SBWriteResGroup5], (instregex "PSHUFLWri")>;
-def: InstRW<[SBWriteResGroup5], (instregex "PSIGNBrr128")>;
-def: InstRW<[SBWriteResGroup5], (instregex "PSIGNDrr128")>;
-def: InstRW<[SBWriteResGroup5], (instregex "PSIGNWrr128")>;
+def: InstRW<[SBWriteResGroup5], (instregex "PSIGNBrr")>;
+def: InstRW<[SBWriteResGroup5], (instregex "PSIGNDrr")>;
+def: InstRW<[SBWriteResGroup5], (instregex "PSIGNWrr")>;
def: InstRW<[SBWriteResGroup5], (instregex "PSLLDQri")>;
def: InstRW<[SBWriteResGroup5], (instregex "PSRLDQri")>;
def: InstRW<[SBWriteResGroup5], (instregex "PSUBBrr")>;
@@ -621,9 +621,9 @@ def: InstRW<[SBWriteResGroup5], (instreg
def: InstRW<[SBWriteResGroup5], (instregex "VPSHUFDri")>;
def: InstRW<[SBWriteResGroup5], (instregex "VPSHUFHWri")>;
def: InstRW<[SBWriteResGroup5], (instregex "VPSHUFLWri")>;
-def: InstRW<[SBWriteResGroup5], (instregex "VPSIGNBrr128")>;
-def: InstRW<[SBWriteResGroup5], (instregex "VPSIGNDrr128")>;
-def: InstRW<[SBWriteResGroup5], (instregex "VPSIGNWrr128")>;
+def: InstRW<[SBWriteResGroup5], (instregex "VPSIGNBrr")>;
+def: InstRW<[SBWriteResGroup5], (instregex "VPSIGNDrr")>;
+def: InstRW<[SBWriteResGroup5], (instregex "VPSIGNWrr")>;
def: InstRW<[SBWriteResGroup5], (instregex "VPSLLDQri")>;
def: InstRW<[SBWriteResGroup5], (instregex "VPSRLDQri")>;
def: InstRW<[SBWriteResGroup5], (instregex "VPSUBBrr")>;
@@ -876,8 +876,8 @@ def SBWriteResGroup20 : SchedWriteRes<[S
let NumMicroOps = 1;
let ResourceCycles = [1];
}
-def: InstRW<[SBWriteResGroup20], (instregex "MMX_PMADDUBSWrr64")>;
-def: InstRW<[SBWriteResGroup20], (instregex "MMX_PMULHRSWrr64")>;
+def: InstRW<[SBWriteResGroup20], (instregex "MMX_PMADDUBSWrr")>;
+def: InstRW<[SBWriteResGroup20], (instregex "MMX_PMULHRSWrr")>;
def: InstRW<[SBWriteResGroup20], (instregex "MMX_PMULUDQirr")>;
def: InstRW<[SBWriteResGroup20], (instregex "PMADDUBSWrr")>;
def: InstRW<[SBWriteResGroup20], (instregex "PMADDWDrr")>;
@@ -1043,23 +1043,23 @@ def SBWriteResGroup24 : SchedWriteRes<[S
let NumMicroOps = 3;
let ResourceCycles = [3];
}
-def: InstRW<[SBWriteResGroup24], (instregex "MMX_PHADDSWrr64")>;
-def: InstRW<[SBWriteResGroup24], (instregex "MMX_PHADDWrr64")>;
-def: InstRW<[SBWriteResGroup24], (instregex "MMX_PHADDrr64")>;
-def: InstRW<[SBWriteResGroup24], (instregex "MMX_PHSUBDrr64")>;
-def: InstRW<[SBWriteResGroup24], (instregex "MMX_PHSUBSWrr64")>;
-def: InstRW<[SBWriteResGroup24], (instregex "MMX_PHSUBWrr64")>;
+def: InstRW<[SBWriteResGroup24], (instregex "MMX_PHADDSWrr")>;
+def: InstRW<[SBWriteResGroup24], (instregex "MMX_PHADDWrr")>;
+def: InstRW<[SBWriteResGroup24], (instregex "MMX_PHADDrr")>;
+def: InstRW<[SBWriteResGroup24], (instregex "MMX_PHSUBDrr")>;
+def: InstRW<[SBWriteResGroup24], (instregex "MMX_PHSUBSWrr")>;
+def: InstRW<[SBWriteResGroup24], (instregex "MMX_PHSUBWrr")>;
def: InstRW<[SBWriteResGroup24], (instregex "PHADDDrr")>;
-def: InstRW<[SBWriteResGroup24], (instregex "PHADDSWrr128")>;
+def: InstRW<[SBWriteResGroup24], (instregex "PHADDSWrr")>;
def: InstRW<[SBWriteResGroup24], (instregex "PHADDWrr")>;
def: InstRW<[SBWriteResGroup24], (instregex "PHSUBDrr")>;
-def: InstRW<[SBWriteResGroup24], (instregex "PHSUBSWrr128")>;
+def: InstRW<[SBWriteResGroup24], (instregex "PHSUBSWrr")>;
def: InstRW<[SBWriteResGroup24], (instregex "PHSUBWrr")>;
def: InstRW<[SBWriteResGroup24], (instregex "VPHADDDrr")>;
-def: InstRW<[SBWriteResGroup24], (instregex "VPHADDSWrr128")>;
+def: InstRW<[SBWriteResGroup24], (instregex "VPHADDSWrr")>;
def: InstRW<[SBWriteResGroup24], (instregex "VPHADDWrr")>;
def: InstRW<[SBWriteResGroup24], (instregex "VPHSUBDrr")>;
-def: InstRW<[SBWriteResGroup24], (instregex "VPHSUBSWrr128")>;
+def: InstRW<[SBWriteResGroup24], (instregex "VPHSUBSWrr")>;
def: InstRW<[SBWriteResGroup24], (instregex "VPHSUBWrr")>;
def SBWriteResGroup25 : SchedWriteRes<[SBPort015]> {
@@ -1177,7 +1177,7 @@ def: InstRW<[SBWriteResGroup30], (instre
def: InstRW<[SBWriteResGroup30], (instregex "MUL_FST0r")>;
def: InstRW<[SBWriteResGroup30], (instregex "MUL_FrST0")>;
def: InstRW<[SBWriteResGroup30], (instregex "PCMPGTQrr")>;
-def: InstRW<[SBWriteResGroup30], (instregex "PHMINPOSUWrr128")>;
+def: InstRW<[SBWriteResGroup30], (instregex "PHMINPOSUWrr")>;
def: InstRW<[SBWriteResGroup30], (instregex "RCPPSr")>;
def: InstRW<[SBWriteResGroup30], (instregex "RCPSSr")>;
def: InstRW<[SBWriteResGroup30], (instregex "RSQRTPSr")>;
@@ -1189,7 +1189,7 @@ def: InstRW<[SBWriteResGroup30], (instre
def: InstRW<[SBWriteResGroup30], (instregex "VMULSDrr")>;
def: InstRW<[SBWriteResGroup30], (instregex "VMULSSrr")>;
def: InstRW<[SBWriteResGroup30], (instregex "VPCMPGTQrr")>;
-def: InstRW<[SBWriteResGroup30], (instregex "VPHMINPOSUWrr128")>;
+def: InstRW<[SBWriteResGroup30], (instregex "VPHMINPOSUWrr")>;
def: InstRW<[SBWriteResGroup30], (instregex "VRCPPSr")>;
def: InstRW<[SBWriteResGroup30], (instregex "VRCPSSr")>;
def: InstRW<[SBWriteResGroup30], (instregex "VRSQRTPSr")>;
@@ -1497,14 +1497,14 @@ def SBWriteResGroup51 : SchedWriteRes<[S
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[SBWriteResGroup51], (instregex "MMX_PABSBrm64")>;
-def: InstRW<[SBWriteResGroup51], (instregex "MMX_PABSDrm64")>;
-def: InstRW<[SBWriteResGroup51], (instregex "MMX_PABSWrm64")>;
-def: InstRW<[SBWriteResGroup51], (instregex "MMX_PALIGNR64irm")>;
-def: InstRW<[SBWriteResGroup51], (instregex "MMX_PSHUFBrm64")>;
-def: InstRW<[SBWriteResGroup51], (instregex "MMX_PSIGNBrm64")>;
-def: InstRW<[SBWriteResGroup51], (instregex "MMX_PSIGNDrm64")>;
-def: InstRW<[SBWriteResGroup51], (instregex "MMX_PSIGNWrm64")>;
+def: InstRW<[SBWriteResGroup51], (instregex "MMX_PABSBrm")>;
+def: InstRW<[SBWriteResGroup51], (instregex "MMX_PABSDrm")>;
+def: InstRW<[SBWriteResGroup51], (instregex "MMX_PABSWrm")>;
+def: InstRW<[SBWriteResGroup51], (instregex "MMX_PALIGNRrmi")>;
+def: InstRW<[SBWriteResGroup51], (instregex "MMX_PSHUFBrm")>;
+def: InstRW<[SBWriteResGroup51], (instregex "MMX_PSIGNBrm")>;
+def: InstRW<[SBWriteResGroup51], (instregex "MMX_PSIGNDrm")>;
+def: InstRW<[SBWriteResGroup51], (instregex "MMX_PSIGNWrm")>;
def SBWriteResGroup52 : SchedWriteRes<[SBPort23,SBPort015]> {
let Latency = 6;
@@ -1709,9 +1709,9 @@ def: InstRW<[SBWriteResGroup59], (instre
def: InstRW<[SBWriteResGroup59], (instregex "PSHUFDmi")>;
def: InstRW<[SBWriteResGroup59], (instregex "PSHUFHWmi")>;
def: InstRW<[SBWriteResGroup59], (instregex "PSHUFLWmi")>;
-def: InstRW<[SBWriteResGroup59], (instregex "PSIGNBrm128")>;
-def: InstRW<[SBWriteResGroup59], (instregex "PSIGNDrm128")>;
-def: InstRW<[SBWriteResGroup59], (instregex "PSIGNWrm128")>;
+def: InstRW<[SBWriteResGroup59], (instregex "PSIGNBrm")>;
+def: InstRW<[SBWriteResGroup59], (instregex "PSIGNDrm")>;
+def: InstRW<[SBWriteResGroup59], (instregex "PSIGNWrm")>;
def: InstRW<[SBWriteResGroup59], (instregex "PSUBBrm")>;
def: InstRW<[SBWriteResGroup59], (instregex "PSUBDrm")>;
def: InstRW<[SBWriteResGroup59], (instregex "PSUBQrm")>;
@@ -1786,9 +1786,9 @@ def: InstRW<[SBWriteResGroup59], (instre
def: InstRW<[SBWriteResGroup59], (instregex "VPSHUFDmi")>;
def: InstRW<[SBWriteResGroup59], (instregex "VPSHUFHWmi")>;
def: InstRW<[SBWriteResGroup59], (instregex "VPSHUFLWmi")>;
-def: InstRW<[SBWriteResGroup59], (instregex "VPSIGNBrm128")>;
-def: InstRW<[SBWriteResGroup59], (instregex "VPSIGNDrm128")>;
-def: InstRW<[SBWriteResGroup59], (instregex "VPSIGNWrm128")>;
+def: InstRW<[SBWriteResGroup59], (instregex "VPSIGNBrm")>;
+def: InstRW<[SBWriteResGroup59], (instregex "VPSIGNDrm")>;
+def: InstRW<[SBWriteResGroup59], (instregex "VPSIGNWrm")>;
def: InstRW<[SBWriteResGroup59], (instregex "VPSUBBrm")>;
def: InstRW<[SBWriteResGroup59], (instregex "VPSUBDrm")>;
def: InstRW<[SBWriteResGroup59], (instregex "VPSUBQrm")>;
@@ -1944,8 +1944,8 @@ def SBWriteResGroup71 : SchedWriteRes<[S
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[SBWriteResGroup71], (instregex "MMX_PMADDUBSWrm64")>;
-def: InstRW<[SBWriteResGroup71], (instregex "MMX_PMULHRSWrm64")>;
+def: InstRW<[SBWriteResGroup71], (instregex "MMX_PMADDUBSWrm")>;
+def: InstRW<[SBWriteResGroup71], (instregex "MMX_PMULHRSWrm")>;
def: InstRW<[SBWriteResGroup71], (instregex "VTESTPDYrm")>;
def: InstRW<[SBWriteResGroup71], (instregex "VTESTPSYrm")>;
@@ -2066,12 +2066,12 @@ def SBWriteResGroup80 : SchedWriteRes<[S
let NumMicroOps = 4;
let ResourceCycles = [1,3];
}
-def: InstRW<[SBWriteResGroup80], (instregex "MMX_PHADDSWrm64")>;
-def: InstRW<[SBWriteResGroup80], (instregex "MMX_PHADDWrm64")>;
-def: InstRW<[SBWriteResGroup80], (instregex "MMX_PHADDrm64")>;
-def: InstRW<[SBWriteResGroup80], (instregex "MMX_PHSUBDrm64")>;
-def: InstRW<[SBWriteResGroup80], (instregex "MMX_PHSUBSWrm64")>;
-def: InstRW<[SBWriteResGroup80], (instregex "MMX_PHSUBWrm64")>;
+def: InstRW<[SBWriteResGroup80], (instregex "MMX_PHADDSWrm")>;
+def: InstRW<[SBWriteResGroup80], (instregex "MMX_PHADDWrm")>;
+def: InstRW<[SBWriteResGroup80], (instregex "MMX_PHADDrm")>;
+def: InstRW<[SBWriteResGroup80], (instregex "MMX_PHSUBDrm")>;
+def: InstRW<[SBWriteResGroup80], (instregex "MMX_PHSUBSWrm")>;
+def: InstRW<[SBWriteResGroup80], (instregex "MMX_PHSUBWrm")>;
def SBWriteResGroup81 : SchedWriteRes<[SBPort23,SBPort015]> {
let Latency = 8;
@@ -2296,16 +2296,16 @@ def SBWriteResGroup96 : SchedWriteRes<[S
let ResourceCycles = [1,3];
}
def: InstRW<[SBWriteResGroup96], (instregex "PHADDDrm")>;
-def: InstRW<[SBWriteResGroup96], (instregex "PHADDSWrm128")>;
+def: InstRW<[SBWriteResGroup96], (instregex "PHADDSWrm")>;
def: InstRW<[SBWriteResGroup96], (instregex "PHADDWrm")>;
def: InstRW<[SBWriteResGroup96], (instregex "PHSUBDrm")>;
-def: InstRW<[SBWriteResGroup96], (instregex "PHSUBSWrm128")>;
+def: InstRW<[SBWriteResGroup96], (instregex "PHSUBSWrm")>;
def: InstRW<[SBWriteResGroup96], (instregex "PHSUBWrm")>;
def: InstRW<[SBWriteResGroup96], (instregex "VPHADDDrm")>;
-def: InstRW<[SBWriteResGroup96], (instregex "VPHADDSWrm128")>;
+def: InstRW<[SBWriteResGroup96], (instregex "VPHADDSWrm")>;
def: InstRW<[SBWriteResGroup96], (instregex "VPHADDWrm")>;
def: InstRW<[SBWriteResGroup96], (instregex "VPHSUBDrm")>;
-def: InstRW<[SBWriteResGroup96], (instregex "VPHSUBSWrm128")>;
+def: InstRW<[SBWriteResGroup96], (instregex "VPHSUBSWrm")>;
def: InstRW<[SBWriteResGroup96], (instregex "VPHSUBWrm")>;
def SBWriteResGroup97 : SchedWriteRes<[SBPort1,SBPort4,SBPort23]> {
@@ -2453,7 +2453,7 @@ def: InstRW<[SBWriteResGroup104], (instr
def: InstRW<[SBWriteResGroup104], (instregex "MULSDrm")>;
def: InstRW<[SBWriteResGroup104], (instregex "MULSSrm")>;
def: InstRW<[SBWriteResGroup104], (instregex "PCMPGTQrm")>;
-def: InstRW<[SBWriteResGroup104], (instregex "PHMINPOSUWrm128")>;
+def: InstRW<[SBWriteResGroup104], (instregex "PHMINPOSUWrm")>;
def: InstRW<[SBWriteResGroup104], (instregex "RCPPSm")>;
def: InstRW<[SBWriteResGroup104], (instregex "RCPSSm")>;
def: InstRW<[SBWriteResGroup104], (instregex "RSQRTPSm")>;
@@ -2463,7 +2463,7 @@ def: InstRW<[SBWriteResGroup104], (instr
def: InstRW<[SBWriteResGroup104], (instregex "VMULSDrm")>;
def: InstRW<[SBWriteResGroup104], (instregex "VMULSSrm")>;
def: InstRW<[SBWriteResGroup104], (instregex "VPCMPGTQrm")>;
-def: InstRW<[SBWriteResGroup104], (instregex "VPHMINPOSUWrm128")>;
+def: InstRW<[SBWriteResGroup104], (instregex "VPHMINPOSUWrm")>;
def: InstRW<[SBWriteResGroup104], (instregex "VRCPPSm")>;
def: InstRW<[SBWriteResGroup104], (instregex "VRCPSSm")>;
def: InstRW<[SBWriteResGroup104], (instregex "VRSQRTPSm")>;
Modified: llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td?rev=323402&r1=323401&r2=323402&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td Wed Jan 24 20:45:30 2018
@@ -366,8 +366,8 @@ def: InstRW<[SKLWriteResGroup3], (instre
def: InstRW<[SKLWriteResGroup3], (instregex "INSERTPSrr")>;
def: InstRW<[SKLWriteResGroup3], (instregex "MMX_MOVD64rr")>;
def: InstRW<[SKLWriteResGroup3], (instregex "MMX_MOVD64to64rr")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "MMX_PALIGNR64irr")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "MMX_PSHUFBrr64")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "MMX_PALIGNRrri")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "MMX_PSHUFBrr")>;
def: InstRW<[SKLWriteResGroup3], (instregex "MMX_PSHUFWri")>;
def: InstRW<[SKLWriteResGroup3], (instregex "MMX_PUNPCKHBWirr")>;
def: InstRW<[SKLWriteResGroup3], (instregex "MMX_PUNPCKHDQirr")>;
@@ -557,9 +557,9 @@ def: InstRW<[SKLWriteResGroup5], (instre
def: InstRW<[SKLWriteResGroup5], (instregex "PMINUBrr")>;
def: InstRW<[SKLWriteResGroup5], (instregex "PMINUDrr")>;
def: InstRW<[SKLWriteResGroup5], (instregex "PMINUWrr")>;
-def: InstRW<[SKLWriteResGroup5], (instregex "PSIGNBrr128")>;
-def: InstRW<[SKLWriteResGroup5], (instregex "PSIGNDrr128")>;
-def: InstRW<[SKLWriteResGroup5], (instregex "PSIGNWrr128")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "PSIGNBrr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "PSIGNDrr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "PSIGNWrr")>;
def: InstRW<[SKLWriteResGroup5], (instregex "PSLLDri")>;
def: InstRW<[SKLWriteResGroup5], (instregex "PSLLQri")>;
def: InstRW<[SKLWriteResGroup5], (instregex "PSLLWri")>;
@@ -628,12 +628,12 @@ def: InstRW<[SKLWriteResGroup5], (instre
def: InstRW<[SKLWriteResGroup5], (instregex "VPMINUDrr")>;
def: InstRW<[SKLWriteResGroup5], (instregex "VPMINUWYrr")>;
def: InstRW<[SKLWriteResGroup5], (instregex "VPMINUWrr")>;
-def: InstRW<[SKLWriteResGroup5], (instregex "VPSIGNBYrr256")>;
-def: InstRW<[SKLWriteResGroup5], (instregex "VPSIGNBrr128")>;
-def: InstRW<[SKLWriteResGroup5], (instregex "VPSIGNDYrr256")>;
-def: InstRW<[SKLWriteResGroup5], (instregex "VPSIGNDrr128")>;
-def: InstRW<[SKLWriteResGroup5], (instregex "VPSIGNWYrr256")>;
-def: InstRW<[SKLWriteResGroup5], (instregex "VPSIGNWrr128")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "VPSIGNBYrr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "VPSIGNBrr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "VPSIGNDYrr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "VPSIGNDrr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "VPSIGNWYrr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "VPSIGNWrr")>;
def: InstRW<[SKLWriteResGroup5], (instregex "VPSLLDYri")>;
def: InstRW<[SKLWriteResGroup5], (instregex "VPSLLDri")>;
def: InstRW<[SKLWriteResGroup5], (instregex "VPSLLQYri")>;
@@ -677,9 +677,9 @@ def SKLWriteResGroup6 : SchedWriteRes<[S
def: InstRW<[SKLWriteResGroup6], (instregex "FINCSTP")>;
def: InstRW<[SKLWriteResGroup6], (instregex "FNOP")>;
def: InstRW<[SKLWriteResGroup6], (instregex "MMX_MOVQ64rr")>;
-def: InstRW<[SKLWriteResGroup6], (instregex "MMX_PABSBrr64")>;
-def: InstRW<[SKLWriteResGroup6], (instregex "MMX_PABSDrr64")>;
-def: InstRW<[SKLWriteResGroup6], (instregex "MMX_PABSWrr64")>;
+def: InstRW<[SKLWriteResGroup6], (instregex "MMX_PABSBrr")>;
+def: InstRW<[SKLWriteResGroup6], (instregex "MMX_PABSDrr")>;
+def: InstRW<[SKLWriteResGroup6], (instregex "MMX_PABSWrr")>;
def: InstRW<[SKLWriteResGroup6], (instregex "MMX_PADDBirr")>;
def: InstRW<[SKLWriteResGroup6], (instregex "MMX_PADDDirr")>;
def: InstRW<[SKLWriteResGroup6], (instregex "MMX_PADDQirr")>;
@@ -687,9 +687,9 @@ def: InstRW<[SKLWriteResGroup6], (instre
def: InstRW<[SKLWriteResGroup6], (instregex "MMX_PANDNirr")>;
def: InstRW<[SKLWriteResGroup6], (instregex "MMX_PANDirr")>;
def: InstRW<[SKLWriteResGroup6], (instregex "MMX_PORirr")>;
-def: InstRW<[SKLWriteResGroup6], (instregex "MMX_PSIGNBrr64")>;
-def: InstRW<[SKLWriteResGroup6], (instregex "MMX_PSIGNDrr64")>;
-def: InstRW<[SKLWriteResGroup6], (instregex "MMX_PSIGNWrr64")>;
+def: InstRW<[SKLWriteResGroup6], (instregex "MMX_PSIGNBrr")>;
+def: InstRW<[SKLWriteResGroup6], (instregex "MMX_PSIGNDrr")>;
+def: InstRW<[SKLWriteResGroup6], (instregex "MMX_PSIGNWrr")>;
def: InstRW<[SKLWriteResGroup6], (instregex "MMX_PSUBBirr")>;
def: InstRW<[SKLWriteResGroup6], (instregex "MMX_PSUBDirr")>;
def: InstRW<[SKLWriteResGroup6], (instregex "MMX_PSUBQirr")>;
@@ -1347,30 +1347,30 @@ def SKLWriteResGroup35 : SchedWriteRes<[
let NumMicroOps = 3;
let ResourceCycles = [1,2];
}
-def: InstRW<[SKLWriteResGroup35], (instregex "MMX_PHADDSWrr64")>;
-def: InstRW<[SKLWriteResGroup35], (instregex "MMX_PHSUBSWrr64")>;
+def: InstRW<[SKLWriteResGroup35], (instregex "MMX_PHADDSWrr")>;
+def: InstRW<[SKLWriteResGroup35], (instregex "MMX_PHSUBSWrr")>;
def SKLWriteResGroup36 : SchedWriteRes<[SKLPort5,SKLPort01]> {
let Latency = 3;
let NumMicroOps = 3;
let ResourceCycles = [2,1];
}
-def: InstRW<[SKLWriteResGroup36], (instregex "PHADDSWrr128")>;
-def: InstRW<[SKLWriteResGroup36], (instregex "PHSUBSWrr128")>;
-def: InstRW<[SKLWriteResGroup36], (instregex "VPHADDSWrr128")>;
-def: InstRW<[SKLWriteResGroup36], (instregex "VPHADDSWrr256")>;
-def: InstRW<[SKLWriteResGroup36], (instregex "VPHSUBSWrr128")>;
-def: InstRW<[SKLWriteResGroup36], (instregex "VPHSUBSWrr256")>;
+def: InstRW<[SKLWriteResGroup36], (instregex "PHADDSWrr")>;
+def: InstRW<[SKLWriteResGroup36], (instregex "PHSUBSWrr")>;
+def: InstRW<[SKLWriteResGroup36], (instregex "VPHADDSWrr")>;
+def: InstRW<[SKLWriteResGroup36], (instregex "VPHADDSWYrr")>;
+def: InstRW<[SKLWriteResGroup36], (instregex "VPHSUBSWrr")>;
+def: InstRW<[SKLWriteResGroup36], (instregex "VPHSUBSWYrr")>;
def SKLWriteResGroup37 : SchedWriteRes<[SKLPort5,SKLPort05]> {
let Latency = 3;
let NumMicroOps = 3;
let ResourceCycles = [2,1];
}
-def: InstRW<[SKLWriteResGroup37], (instregex "MMX_PHADDWrr64")>;
-def: InstRW<[SKLWriteResGroup37], (instregex "MMX_PHADDrr64")>;
-def: InstRW<[SKLWriteResGroup37], (instregex "MMX_PHSUBDrr64")>;
-def: InstRW<[SKLWriteResGroup37], (instregex "MMX_PHSUBWrr64")>;
+def: InstRW<[SKLWriteResGroup37], (instregex "MMX_PHADDWrr")>;
+def: InstRW<[SKLWriteResGroup37], (instregex "MMX_PHADDrr")>;
+def: InstRW<[SKLWriteResGroup37], (instregex "MMX_PHSUBDrr")>;
+def: InstRW<[SKLWriteResGroup37], (instregex "MMX_PHSUBWrr")>;
def SKLWriteResGroup38 : SchedWriteRes<[SKLPort5,SKLPort015]> {
let Latency = 3;
@@ -1464,9 +1464,9 @@ def: InstRW<[SKLWriteResGroup47], (instr
def: InstRW<[SKLWriteResGroup47], (instregex "AESDECrr")>;
def: InstRW<[SKLWriteResGroup47], (instregex "AESENCLASTrr")>;
def: InstRW<[SKLWriteResGroup47], (instregex "AESENCrr")>;
-def: InstRW<[SKLWriteResGroup47], (instregex "MMX_PMADDUBSWrr64")>;
+def: InstRW<[SKLWriteResGroup47], (instregex "MMX_PMADDUBSWrr")>;
def: InstRW<[SKLWriteResGroup47], (instregex "MMX_PMADDWDirr")>;
-def: InstRW<[SKLWriteResGroup47], (instregex "MMX_PMULHRSWrr64")>;
+def: InstRW<[SKLWriteResGroup47], (instregex "MMX_PMULHRSWrr")>;
def: InstRW<[SKLWriteResGroup47], (instregex "MMX_PMULHUWirr")>;
def: InstRW<[SKLWriteResGroup47], (instregex "MMX_PMULHWirr")>;
def: InstRW<[SKLWriteResGroup47], (instregex "MMX_PMULLWirr")>;
@@ -1555,7 +1555,7 @@ def: InstRW<[SKLWriteResGroup49], (instr
def: InstRW<[SKLWriteResGroup49], (instregex "MIN(C?)PSrr")>;
def: InstRW<[SKLWriteResGroup49], (instregex "MIN(C?)SDrr")>;
def: InstRW<[SKLWriteResGroup49], (instregex "MIN(C?)SSrr")>;
-def: InstRW<[SKLWriteResGroup49], (instregex "PHMINPOSUWrr128")>;
+def: InstRW<[SKLWriteResGroup49], (instregex "PHMINPOSUWrr")>;
def: InstRW<[SKLWriteResGroup49], (instregex "PMADDUBSWrr")>;
def: InstRW<[SKLWriteResGroup49], (instregex "PMADDWDrr")>;
def: InstRW<[SKLWriteResGroup49], (instregex "PMULDQrr")>;
@@ -1588,7 +1588,7 @@ def: InstRW<[SKLWriteResGroup49], (instr
def: InstRW<[SKLWriteResGroup49], (instregex "VMIN(C?)PSrr")>;
def: InstRW<[SKLWriteResGroup49], (instregex "VMIN(C?)SDrr")>;
def: InstRW<[SKLWriteResGroup49], (instregex "VMIN(C?)SSrr")>;
-def: InstRW<[SKLWriteResGroup49], (instregex "VPHMINPOSUWrr128")>;
+def: InstRW<[SKLWriteResGroup49], (instregex "VPHMINPOSUWrr")>;
def: InstRW<[SKLWriteResGroup49], (instregex "VPMADDUBSWYrr")>;
def: InstRW<[SKLWriteResGroup49], (instregex "VPMADDUBSWrr")>;
def: InstRW<[SKLWriteResGroup49], (instregex "VPMADDWDYrr")>;
@@ -1899,9 +1899,9 @@ def SKLWriteResGroup71 : SchedWriteRes<[
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[SKLWriteResGroup71], (instregex "MMX_PALIGNR64irm")>;
+def: InstRW<[SKLWriteResGroup71], (instregex "MMX_PALIGNRrmi")>;
def: InstRW<[SKLWriteResGroup71], (instregex "MMX_PINSRWrm")>;
-def: InstRW<[SKLWriteResGroup71], (instregex "MMX_PSHUFBrm64")>;
+def: InstRW<[SKLWriteResGroup71], (instregex "MMX_PSHUFBrm")>;
def: InstRW<[SKLWriteResGroup71], (instregex "MMX_PSHUFWmi")>;
def: InstRW<[SKLWriteResGroup71], (instregex "MMX_PUNPCKHBWirm")>;
def: InstRW<[SKLWriteResGroup71], (instregex "MMX_PUNPCKHDQirm")>;
@@ -1963,9 +1963,9 @@ def SKLWriteResGroup73 : SchedWriteRes<[
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[SKLWriteResGroup73], (instregex "MMX_PABSBrm64")>;
-def: InstRW<[SKLWriteResGroup73], (instregex "MMX_PABSDrm64")>;
-def: InstRW<[SKLWriteResGroup73], (instregex "MMX_PABSWrm64")>;
+def: InstRW<[SKLWriteResGroup73], (instregex "MMX_PABSBrm")>;
+def: InstRW<[SKLWriteResGroup73], (instregex "MMX_PABSDrm")>;
+def: InstRW<[SKLWriteResGroup73], (instregex "MMX_PABSWrm")>;
def: InstRW<[SKLWriteResGroup73], (instregex "MMX_PADDBirm")>;
def: InstRW<[SKLWriteResGroup73], (instregex "MMX_PADDDirm")>;
def: InstRW<[SKLWriteResGroup73], (instregex "MMX_PADDQirm")>;
@@ -1973,9 +1973,9 @@ def: InstRW<[SKLWriteResGroup73], (instr
def: InstRW<[SKLWriteResGroup73], (instregex "MMX_PANDNirm")>;
def: InstRW<[SKLWriteResGroup73], (instregex "MMX_PANDirm")>;
def: InstRW<[SKLWriteResGroup73], (instregex "MMX_PORirm")>;
-def: InstRW<[SKLWriteResGroup73], (instregex "MMX_PSIGNBrm64")>;
-def: InstRW<[SKLWriteResGroup73], (instregex "MMX_PSIGNDrm64")>;
-def: InstRW<[SKLWriteResGroup73], (instregex "MMX_PSIGNWrm64")>;
+def: InstRW<[SKLWriteResGroup73], (instregex "MMX_PSIGNBrm")>;
+def: InstRW<[SKLWriteResGroup73], (instregex "MMX_PSIGNDrm")>;
+def: InstRW<[SKLWriteResGroup73], (instregex "MMX_PSIGNWrm")>;
def: InstRW<[SKLWriteResGroup73], (instregex "MMX_PSUBBirm")>;
def: InstRW<[SKLWriteResGroup73], (instregex "MMX_PSUBDirm")>;
def: InstRW<[SKLWriteResGroup73], (instregex "MMX_PSUBQirm")>;
@@ -2308,9 +2308,9 @@ def: InstRW<[SKLWriteResGroup90], (instr
def: InstRW<[SKLWriteResGroup90], (instregex "PMINUBrm")>;
def: InstRW<[SKLWriteResGroup90], (instregex "PMINUDrm")>;
def: InstRW<[SKLWriteResGroup90], (instregex "PMINUWrm")>;
-def: InstRW<[SKLWriteResGroup90], (instregex "PSIGNBrm128")>;
-def: InstRW<[SKLWriteResGroup90], (instregex "PSIGNDrm128")>;
-def: InstRW<[SKLWriteResGroup90], (instregex "PSIGNWrm128")>;
+def: InstRW<[SKLWriteResGroup90], (instregex "PSIGNBrm")>;
+def: InstRW<[SKLWriteResGroup90], (instregex "PSIGNDrm")>;
+def: InstRW<[SKLWriteResGroup90], (instregex "PSIGNWrm")>;
def: InstRW<[SKLWriteResGroup90], (instregex "PSLLDrm")>;
def: InstRW<[SKLWriteResGroup90], (instregex "PSLLQrm")>;
def: InstRW<[SKLWriteResGroup90], (instregex "PSLLWrm")>;
@@ -2351,9 +2351,9 @@ def: InstRW<[SKLWriteResGroup90], (instr
def: InstRW<[SKLWriteResGroup90], (instregex "VPMINUBrm")>;
def: InstRW<[SKLWriteResGroup90], (instregex "VPMINUDrm")>;
def: InstRW<[SKLWriteResGroup90], (instregex "VPMINUWrm")>;
-def: InstRW<[SKLWriteResGroup90], (instregex "VPSIGNBrm128")>;
-def: InstRW<[SKLWriteResGroup90], (instregex "VPSIGNDrm128")>;
-def: InstRW<[SKLWriteResGroup90], (instregex "VPSIGNWrm128")>;
+def: InstRW<[SKLWriteResGroup90], (instregex "VPSIGNBrm")>;
+def: InstRW<[SKLWriteResGroup90], (instregex "VPSIGNDrm")>;
+def: InstRW<[SKLWriteResGroup90], (instregex "VPSIGNWrm")>;
def: InstRW<[SKLWriteResGroup90], (instregex "VPSLLDrm")>;
def: InstRW<[SKLWriteResGroup90], (instregex "VPSLLQrm")>;
def: InstRW<[SKLWriteResGroup90], (instregex "VPSLLVDrm")>;
@@ -2685,9 +2685,9 @@ def: InstRW<[SKLWriteResGroup109], (inst
def: InstRW<[SKLWriteResGroup109], (instregex "VPMINUBYrm")>;
def: InstRW<[SKLWriteResGroup109], (instregex "VPMINUDYrm")>;
def: InstRW<[SKLWriteResGroup109], (instregex "VPMINUWYrm")>;
-def: InstRW<[SKLWriteResGroup109], (instregex "VPSIGNBYrm256")>;
-def: InstRW<[SKLWriteResGroup109], (instregex "VPSIGNDYrm256")>;
-def: InstRW<[SKLWriteResGroup109], (instregex "VPSIGNWYrm256")>;
+def: InstRW<[SKLWriteResGroup109], (instregex "VPSIGNBYrm")>;
+def: InstRW<[SKLWriteResGroup109], (instregex "VPSIGNDYrm")>;
+def: InstRW<[SKLWriteResGroup109], (instregex "VPSIGNWYrm")>;
def: InstRW<[SKLWriteResGroup109], (instregex "VPSLLDYrm")>;
def: InstRW<[SKLWriteResGroup109], (instregex "VPSLLQYrm")>;
def: InstRW<[SKLWriteResGroup109], (instregex "VPSLLVDYrm")>;
@@ -2757,18 +2757,18 @@ def SKLWriteResGroup112 : SchedWriteRes<
let NumMicroOps = 4;
let ResourceCycles = [1,2,1];
}
-def: InstRW<[SKLWriteResGroup112], (instregex "MMX_PHADDSWrm64")>;
-def: InstRW<[SKLWriteResGroup112], (instregex "MMX_PHSUBSWrm64")>;
+def: InstRW<[SKLWriteResGroup112], (instregex "MMX_PHADDSWrm")>;
+def: InstRW<[SKLWriteResGroup112], (instregex "MMX_PHSUBSWrm")>;
def SKLWriteResGroup113 : SchedWriteRes<[SKLPort5,SKLPort23,SKLPort05]> {
let Latency = 8;
let NumMicroOps = 4;
let ResourceCycles = [2,1,1];
}
-def: InstRW<[SKLWriteResGroup113], (instregex "MMX_PHADDWrm64")>;
-def: InstRW<[SKLWriteResGroup113], (instregex "MMX_PHADDrm64")>;
-def: InstRW<[SKLWriteResGroup113], (instregex "MMX_PHSUBDrm64")>;
-def: InstRW<[SKLWriteResGroup113], (instregex "MMX_PHSUBWrm64")>;
+def: InstRW<[SKLWriteResGroup113], (instregex "MMX_PHADDWrm")>;
+def: InstRW<[SKLWriteResGroup113], (instregex "MMX_PHADDrm")>;
+def: InstRW<[SKLWriteResGroup113], (instregex "MMX_PHSUBDrm")>;
+def: InstRW<[SKLWriteResGroup113], (instregex "MMX_PHSUBWrm")>;
def SKLWriteResGroup114 : SchedWriteRes<[SKLPort4,SKLPort5,SKLPort237,SKLPort015]> {
let Latency = 8;
@@ -2841,9 +2841,9 @@ def SKLWriteResGroup120 : SchedWriteRes<
let ResourceCycles = [1,1];
}
def: InstRW<[SKLWriteResGroup120], (instregex "MMX_CVTPI2PSirm")>;
-def: InstRW<[SKLWriteResGroup120], (instregex "MMX_PMADDUBSWrm64")>;
+def: InstRW<[SKLWriteResGroup120], (instregex "MMX_PMADDUBSWrm")>;
def: InstRW<[SKLWriteResGroup120], (instregex "MMX_PMADDWDirm")>;
-def: InstRW<[SKLWriteResGroup120], (instregex "MMX_PMULHRSWrm64")>;
+def: InstRW<[SKLWriteResGroup120], (instregex "MMX_PMULHRSWrm")>;
def: InstRW<[SKLWriteResGroup120], (instregex "MMX_PMULHUWirm")>;
def: InstRW<[SKLWriteResGroup120], (instregex "MMX_PMULHWirm")>;
def: InstRW<[SKLWriteResGroup120], (instregex "MMX_PMULLWirm")>;
@@ -2948,10 +2948,10 @@ def SKLWriteResGroup128 : SchedWriteRes<
let NumMicroOps = 4;
let ResourceCycles = [2,1,1];
}
-def: InstRW<[SKLWriteResGroup128], (instregex "PHADDSWrm128")>;
-def: InstRW<[SKLWriteResGroup128], (instregex "PHSUBSWrm128")>;
-def: InstRW<[SKLWriteResGroup128], (instregex "VPHADDSWrm128")>;
-def: InstRW<[SKLWriteResGroup128], (instregex "VPHSUBSWrm128")>;
+def: InstRW<[SKLWriteResGroup128], (instregex "PHADDSWrm")>;
+def: InstRW<[SKLWriteResGroup128], (instregex "PHSUBSWrm")>;
+def: InstRW<[SKLWriteResGroup128], (instregex "VPHADDSWrm")>;
+def: InstRW<[SKLWriteResGroup128], (instregex "VPHSUBSWrm")>;
def SKLWriteResGroup129 : SchedWriteRes<[SKLPort5,SKLPort23,SKLPort015]> {
let Latency = 9;
@@ -3068,7 +3068,7 @@ def: InstRW<[SKLWriteResGroup135], (inst
def: InstRW<[SKLWriteResGroup135], (instregex "MAX(C?)PSrm")>;
def: InstRW<[SKLWriteResGroup135], (instregex "MIN(C?)PDrm")>;
def: InstRW<[SKLWriteResGroup135], (instregex "MIN(C?)PSrm")>;
-def: InstRW<[SKLWriteResGroup135], (instregex "PHMINPOSUWrm128")>;
+def: InstRW<[SKLWriteResGroup135], (instregex "PHMINPOSUWrm")>;
def: InstRW<[SKLWriteResGroup135], (instregex "PMADDUBSWrm")>;
def: InstRW<[SKLWriteResGroup135], (instregex "PMADDWDrm")>;
def: InstRW<[SKLWriteResGroup135], (instregex "PMULDQrm")>;
@@ -3088,7 +3088,7 @@ def: InstRW<[SKLWriteResGroup135], (inst
def: InstRW<[SKLWriteResGroup135], (instregex "VMAX(C?)PSrm")>;
def: InstRW<[SKLWriteResGroup135], (instregex "VMIN(C?)PDrm")>;
def: InstRW<[SKLWriteResGroup135], (instregex "VMIN(C?)PSrm")>;
-def: InstRW<[SKLWriteResGroup135], (instregex "VPHMINPOSUWrm128")>;
+def: InstRW<[SKLWriteResGroup135], (instregex "VPHMINPOSUWrm")>;
def: InstRW<[SKLWriteResGroup135], (instregex "VPMADDUBSWrm")>;
def: InstRW<[SKLWriteResGroup135], (instregex "VPMADDWDrm")>;
def: InstRW<[SKLWriteResGroup135], (instregex "VPMULDQrm")>;
@@ -3137,8 +3137,8 @@ def SKLWriteResGroup140 : SchedWriteRes<
let NumMicroOps = 4;
let ResourceCycles = [2,1,1];
}
-def: InstRW<[SKLWriteResGroup140], (instregex "VPHADDSWrm256")>;
-def: InstRW<[SKLWriteResGroup140], (instregex "VPHSUBSWrm256")>;
+def: InstRW<[SKLWriteResGroup140], (instregex "VPHADDSWYrm")>;
+def: InstRW<[SKLWriteResGroup140], (instregex "VPHSUBSWYrm")>;
def SKLWriteResGroup141 : SchedWriteRes<[SKLPort5,SKLPort23,SKLPort015]> {
let Latency = 10;
Modified: llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td?rev=323402&r1=323401&r2=323402&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td Wed Jan 24 20:45:30 2018
@@ -410,8 +410,8 @@ def: InstRW<[SKXWriteResGroup3], (instre
def: InstRW<[SKXWriteResGroup3], (instregex "KMOVWkr")>;
def: InstRW<[SKXWriteResGroup3], (instregex "MMX_MOVD64rr")>;
def: InstRW<[SKXWriteResGroup3], (instregex "MMX_MOVD64to64rr")>;
-def: InstRW<[SKXWriteResGroup3], (instregex "MMX_PALIGNR64irr")>;
-def: InstRW<[SKXWriteResGroup3], (instregex "MMX_PSHUFBrr64")>;
+def: InstRW<[SKXWriteResGroup3], (instregex "MMX_PALIGNRrri")>;
+def: InstRW<[SKXWriteResGroup3], (instregex "MMX_PSHUFBrr")>;
def: InstRW<[SKXWriteResGroup3], (instregex "MMX_PSHUFWri")>;
def: InstRW<[SKXWriteResGroup3], (instregex "MMX_PUNPCKHBWirr")>;
def: InstRW<[SKXWriteResGroup3], (instregex "MMX_PUNPCKHDQirr")>;
@@ -705,9 +705,9 @@ def: InstRW<[SKXWriteResGroup5], (instre
def: InstRW<[SKXWriteResGroup5], (instregex "PMINUBrr")>;
def: InstRW<[SKXWriteResGroup5], (instregex "PMINUDrr")>;
def: InstRW<[SKXWriteResGroup5], (instregex "PMINUWrr")>;
-def: InstRW<[SKXWriteResGroup5], (instregex "PSIGNBrr128")>;
-def: InstRW<[SKXWriteResGroup5], (instregex "PSIGNDrr128")>;
-def: InstRW<[SKXWriteResGroup5], (instregex "PSIGNWrr128")>;
+def: InstRW<[SKXWriteResGroup5], (instregex "PSIGNBrr")>;
+def: InstRW<[SKXWriteResGroup5], (instregex "PSIGNDrr")>;
+def: InstRW<[SKXWriteResGroup5], (instregex "PSIGNWrr")>;
def: InstRW<[SKXWriteResGroup5], (instregex "PSLLDri")>;
def: InstRW<[SKXWriteResGroup5], (instregex "PSLLQri")>;
def: InstRW<[SKXWriteResGroup5], (instregex "PSLLWri")>;
@@ -866,12 +866,12 @@ def: InstRW<[SKXWriteResGroup5], (instre
def: InstRW<[SKXWriteResGroup5], (instregex "VPRORVQZ128rr(b?)(k?)(z?)")>;
def: InstRW<[SKXWriteResGroup5], (instregex "VPRORVQZ256rr(b?)(k?)(z?)")>;
def: InstRW<[SKXWriteResGroup5], (instregex "VPRORVQZrr(b?)(k?)(z?)")>;
-def: InstRW<[SKXWriteResGroup5], (instregex "VPSIGNBYrr256")>;
-def: InstRW<[SKXWriteResGroup5], (instregex "VPSIGNBrr128")>;
-def: InstRW<[SKXWriteResGroup5], (instregex "VPSIGNDYrr256")>;
-def: InstRW<[SKXWriteResGroup5], (instregex "VPSIGNDrr128")>;
-def: InstRW<[SKXWriteResGroup5], (instregex "VPSIGNWYrr256")>;
-def: InstRW<[SKXWriteResGroup5], (instregex "VPSIGNWrr128")>;
+def: InstRW<[SKXWriteResGroup5], (instregex "VPSIGNBYrr")>;
+def: InstRW<[SKXWriteResGroup5], (instregex "VPSIGNBrr")>;
+def: InstRW<[SKXWriteResGroup5], (instregex "VPSIGNDYrr")>;
+def: InstRW<[SKXWriteResGroup5], (instregex "VPSIGNDrr")>;
+def: InstRW<[SKXWriteResGroup5], (instregex "VPSIGNWYrr")>;
+def: InstRW<[SKXWriteResGroup5], (instregex "VPSIGNWrr")>;
def: InstRW<[SKXWriteResGroup5], (instregex "VPSLLDYri")>;
def: InstRW<[SKXWriteResGroup5], (instregex "VPSLLDZ128r(b?)i(k?)(z?)")>;
def: InstRW<[SKXWriteResGroup5], (instregex "VPSLLDZ256r(b?)i(k?)(z?)")>;
@@ -981,9 +981,9 @@ def SKXWriteResGroup6 : SchedWriteRes<[S
def: InstRW<[SKXWriteResGroup6], (instregex "FINCSTP")>;
def: InstRW<[SKXWriteResGroup6], (instregex "FNOP")>;
def: InstRW<[SKXWriteResGroup6], (instregex "MMX_MOVQ64rr")>;
-def: InstRW<[SKXWriteResGroup6], (instregex "MMX_PABSBrr64")>;
-def: InstRW<[SKXWriteResGroup6], (instregex "MMX_PABSDrr64")>;
-def: InstRW<[SKXWriteResGroup6], (instregex "MMX_PABSWrr64")>;
+def: InstRW<[SKXWriteResGroup6], (instregex "MMX_PABSBrr")>;
+def: InstRW<[SKXWriteResGroup6], (instregex "MMX_PABSDrr")>;
+def: InstRW<[SKXWriteResGroup6], (instregex "MMX_PABSWrr")>;
def: InstRW<[SKXWriteResGroup6], (instregex "MMX_PADDBirr")>;
def: InstRW<[SKXWriteResGroup6], (instregex "MMX_PADDDirr")>;
def: InstRW<[SKXWriteResGroup6], (instregex "MMX_PADDQirr")>;
@@ -991,9 +991,9 @@ def: InstRW<[SKXWriteResGroup6], (instre
def: InstRW<[SKXWriteResGroup6], (instregex "MMX_PANDNirr")>;
def: InstRW<[SKXWriteResGroup6], (instregex "MMX_PANDirr")>;
def: InstRW<[SKXWriteResGroup6], (instregex "MMX_PORirr")>;
-def: InstRW<[SKXWriteResGroup6], (instregex "MMX_PSIGNBrr64")>;
-def: InstRW<[SKXWriteResGroup6], (instregex "MMX_PSIGNDrr64")>;
-def: InstRW<[SKXWriteResGroup6], (instregex "MMX_PSIGNWrr64")>;
+def: InstRW<[SKXWriteResGroup6], (instregex "MMX_PSIGNBrr")>;
+def: InstRW<[SKXWriteResGroup6], (instregex "MMX_PSIGNDrr")>;
+def: InstRW<[SKXWriteResGroup6], (instregex "MMX_PSIGNWrr")>;
def: InstRW<[SKXWriteResGroup6], (instregex "MMX_PSUBBirr")>;
def: InstRW<[SKXWriteResGroup6], (instregex "MMX_PSUBDirr")>;
def: InstRW<[SKXWriteResGroup6], (instregex "MMX_PSUBQirr")>;
@@ -2153,30 +2153,30 @@ def SKXWriteResGroup37 : SchedWriteRes<[
let NumMicroOps = 3;
let ResourceCycles = [1,2];
}
-def: InstRW<[SKXWriteResGroup37], (instregex "MMX_PHADDSWrr64")>;
-def: InstRW<[SKXWriteResGroup37], (instregex "MMX_PHSUBSWrr64")>;
+def: InstRW<[SKXWriteResGroup37], (instregex "MMX_PHADDSWrr")>;
+def: InstRW<[SKXWriteResGroup37], (instregex "MMX_PHSUBSWrr")>;
def SKXWriteResGroup38 : SchedWriteRes<[SKXPort5,SKXPort01]> {
let Latency = 3;
let NumMicroOps = 3;
let ResourceCycles = [2,1];
}
-def: InstRW<[SKXWriteResGroup38], (instregex "PHADDSWrr128")>;
-def: InstRW<[SKXWriteResGroup38], (instregex "PHSUBSWrr128")>;
-def: InstRW<[SKXWriteResGroup38], (instregex "VPHADDSWrr128")>;
-def: InstRW<[SKXWriteResGroup38], (instregex "VPHADDSWrr256")>;
-def: InstRW<[SKXWriteResGroup38], (instregex "VPHSUBSWrr128")>;
-def: InstRW<[SKXWriteResGroup38], (instregex "VPHSUBSWrr256")>;
+def: InstRW<[SKXWriteResGroup38], (instregex "PHADDSWrr")>;
+def: InstRW<[SKXWriteResGroup38], (instregex "PHSUBSWrr")>;
+def: InstRW<[SKXWriteResGroup38], (instregex "VPHADDSWrr")>;
+def: InstRW<[SKXWriteResGroup38], (instregex "VPHADDSWYrr")>;
+def: InstRW<[SKXWriteResGroup38], (instregex "VPHSUBSWrr")>;
+def: InstRW<[SKXWriteResGroup38], (instregex "VPHSUBSWYrr")>;
def SKXWriteResGroup39 : SchedWriteRes<[SKXPort5,SKXPort05]> {
let Latency = 3;
let NumMicroOps = 3;
let ResourceCycles = [2,1];
}
-def: InstRW<[SKXWriteResGroup39], (instregex "MMX_PHADDWrr64")>;
-def: InstRW<[SKXWriteResGroup39], (instregex "MMX_PHADDrr64")>;
-def: InstRW<[SKXWriteResGroup39], (instregex "MMX_PHSUBDrr64")>;
-def: InstRW<[SKXWriteResGroup39], (instregex "MMX_PHSUBWrr64")>;
+def: InstRW<[SKXWriteResGroup39], (instregex "MMX_PHADDWrr")>;
+def: InstRW<[SKXWriteResGroup39], (instregex "MMX_PHADDrr")>;
+def: InstRW<[SKXWriteResGroup39], (instregex "MMX_PHSUBDrr")>;
+def: InstRW<[SKXWriteResGroup39], (instregex "MMX_PHSUBWrr")>;
def SKXWriteResGroup40 : SchedWriteRes<[SKXPort5,SKXPort015]> {
let Latency = 3;
@@ -2270,9 +2270,9 @@ def: InstRW<[SKXWriteResGroup49], (instr
def: InstRW<[SKXWriteResGroup49], (instregex "AESDECrr")>;
def: InstRW<[SKXWriteResGroup49], (instregex "AESENCLASTrr")>;
def: InstRW<[SKXWriteResGroup49], (instregex "AESENCrr")>;
-def: InstRW<[SKXWriteResGroup49], (instregex "MMX_PMADDUBSWrr64")>;
+def: InstRW<[SKXWriteResGroup49], (instregex "MMX_PMADDUBSWrr")>;
def: InstRW<[SKXWriteResGroup49], (instregex "MMX_PMADDWDirr")>;
-def: InstRW<[SKXWriteResGroup49], (instregex "MMX_PMULHRSWrr64")>;
+def: InstRW<[SKXWriteResGroup49], (instregex "MMX_PMULHRSWrr")>;
def: InstRW<[SKXWriteResGroup49], (instregex "MMX_PMULHUWirr")>;
def: InstRW<[SKXWriteResGroup49], (instregex "MMX_PMULHWirr")>;
def: InstRW<[SKXWriteResGroup49], (instregex "MMX_PMULLWirr")>;
@@ -2337,7 +2337,7 @@ def: InstRW<[SKXWriteResGroup50], (instr
def: InstRW<[SKXWriteResGroup50], (instregex "MULPSrr")>;
def: InstRW<[SKXWriteResGroup50], (instregex "MULSDrr")>;
def: InstRW<[SKXWriteResGroup50], (instregex "MULSSrr")>;
-def: InstRW<[SKXWriteResGroup50], (instregex "PHMINPOSUWrr128")>;
+def: InstRW<[SKXWriteResGroup50], (instregex "PHMINPOSUWrr")>;
def: InstRW<[SKXWriteResGroup50], (instregex "PMADDUBSWrr")>;
def: InstRW<[SKXWriteResGroup50], (instregex "PMADDWDrr")>;
def: InstRW<[SKXWriteResGroup50], (instregex "PMULDQrr")>;
@@ -2491,7 +2491,7 @@ def: InstRW<[SKXWriteResGroup50], (instr
def: InstRW<[SKXWriteResGroup50], (instregex "VMULSDrr")>;
def: InstRW<[SKXWriteResGroup50], (instregex "VMULSSZrr(b?)(_Int)?(k?)(z?)")>;
def: InstRW<[SKXWriteResGroup50], (instregex "VMULSSrr")>;
-def: InstRW<[SKXWriteResGroup50], (instregex "VPHMINPOSUWrr128")>;
+def: InstRW<[SKXWriteResGroup50], (instregex "VPHMINPOSUWrr")>;
def: InstRW<[SKXWriteResGroup50], (instregex "VPLZCNTDZ128rr(b?)(k?)(z?)")>;
def: InstRW<[SKXWriteResGroup50], (instregex "VPLZCNTDZ256rr(b?)(k?)(z?)")>;
def: InstRW<[SKXWriteResGroup50], (instregex "VPLZCNTDZrr(b?)(k?)(z?)")>;
@@ -3075,9 +3075,9 @@ def SKXWriteResGroup75 : SchedWriteRes<[
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[SKXWriteResGroup75], (instregex "MMX_PALIGNR64irm")>;
+def: InstRW<[SKXWriteResGroup75], (instregex "MMX_PALIGNRrmi")>;
def: InstRW<[SKXWriteResGroup75], (instregex "MMX_PINSRWrm")>;
-def: InstRW<[SKXWriteResGroup75], (instregex "MMX_PSHUFBrm64")>;
+def: InstRW<[SKXWriteResGroup75], (instregex "MMX_PSHUFBrm")>;
def: InstRW<[SKXWriteResGroup75], (instregex "MMX_PSHUFWmi")>;
def: InstRW<[SKXWriteResGroup75], (instregex "MMX_PUNPCKHBWirm")>;
def: InstRW<[SKXWriteResGroup75], (instregex "MMX_PUNPCKHDQirm")>;
@@ -3147,9 +3147,9 @@ def SKXWriteResGroup77 : SchedWriteRes<[
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[SKXWriteResGroup77], (instregex "MMX_PABSBrm64")>;
-def: InstRW<[SKXWriteResGroup77], (instregex "MMX_PABSDrm64")>;
-def: InstRW<[SKXWriteResGroup77], (instregex "MMX_PABSWrm64")>;
+def: InstRW<[SKXWriteResGroup77], (instregex "MMX_PABSBrm")>;
+def: InstRW<[SKXWriteResGroup77], (instregex "MMX_PABSDrm")>;
+def: InstRW<[SKXWriteResGroup77], (instregex "MMX_PABSWrm")>;
def: InstRW<[SKXWriteResGroup77], (instregex "MMX_PADDBirm")>;
def: InstRW<[SKXWriteResGroup77], (instregex "MMX_PADDDirm")>;
def: InstRW<[SKXWriteResGroup77], (instregex "MMX_PADDQirm")>;
@@ -3157,9 +3157,9 @@ def: InstRW<[SKXWriteResGroup77], (instr
def: InstRW<[SKXWriteResGroup77], (instregex "MMX_PANDNirm")>;
def: InstRW<[SKXWriteResGroup77], (instregex "MMX_PANDirm")>;
def: InstRW<[SKXWriteResGroup77], (instregex "MMX_PORirm")>;
-def: InstRW<[SKXWriteResGroup77], (instregex "MMX_PSIGNBrm64")>;
-def: InstRW<[SKXWriteResGroup77], (instregex "MMX_PSIGNDrm64")>;
-def: InstRW<[SKXWriteResGroup77], (instregex "MMX_PSIGNWrm64")>;
+def: InstRW<[SKXWriteResGroup77], (instregex "MMX_PSIGNBrm")>;
+def: InstRW<[SKXWriteResGroup77], (instregex "MMX_PSIGNDrm")>;
+def: InstRW<[SKXWriteResGroup77], (instregex "MMX_PSIGNWrm")>;
def: InstRW<[SKXWriteResGroup77], (instregex "MMX_PSUBBirm")>;
def: InstRW<[SKXWriteResGroup77], (instregex "MMX_PSUBDirm")>;
def: InstRW<[SKXWriteResGroup77], (instregex "MMX_PSUBQirm")>;
@@ -3563,9 +3563,9 @@ def: InstRW<[SKXWriteResGroup94], (instr
def: InstRW<[SKXWriteResGroup94], (instregex "PMINUBrm")>;
def: InstRW<[SKXWriteResGroup94], (instregex "PMINUDrm")>;
def: InstRW<[SKXWriteResGroup94], (instregex "PMINUWrm")>;
-def: InstRW<[SKXWriteResGroup94], (instregex "PSIGNBrm128")>;
-def: InstRW<[SKXWriteResGroup94], (instregex "PSIGNDrm128")>;
-def: InstRW<[SKXWriteResGroup94], (instregex "PSIGNWrm128")>;
+def: InstRW<[SKXWriteResGroup94], (instregex "PSIGNBrm")>;
+def: InstRW<[SKXWriteResGroup94], (instregex "PSIGNDrm")>;
+def: InstRW<[SKXWriteResGroup94], (instregex "PSIGNWrm")>;
def: InstRW<[SKXWriteResGroup94], (instregex "PSLLDrm")>;
def: InstRW<[SKXWriteResGroup94], (instregex "PSLLQrm")>;
def: InstRW<[SKXWriteResGroup94], (instregex "PSLLWrm")>;
@@ -3636,9 +3636,9 @@ def: InstRW<[SKXWriteResGroup94], (instr
def: InstRW<[SKXWriteResGroup94], (instregex "VPRORQZ128m(b?)i(k?)(z?)")>;
def: InstRW<[SKXWriteResGroup94], (instregex "VPRORVDZ128rm(b?)(k?)(z?)")>;
def: InstRW<[SKXWriteResGroup94], (instregex "VPRORVQZ128rm(b?)(k?)(z?)")>;
-def: InstRW<[SKXWriteResGroup94], (instregex "VPSIGNBrm128")>;
-def: InstRW<[SKXWriteResGroup94], (instregex "VPSIGNDrm128")>;
-def: InstRW<[SKXWriteResGroup94], (instregex "VPSIGNWrm128")>;
+def: InstRW<[SKXWriteResGroup94], (instregex "VPSIGNBrm")>;
+def: InstRW<[SKXWriteResGroup94], (instregex "VPSIGNDrm")>;
+def: InstRW<[SKXWriteResGroup94], (instregex "VPSIGNWrm")>;
def: InstRW<[SKXWriteResGroup94], (instregex "VPSLLDZ128m(b?)i(k?)(z?)")>;
def: InstRW<[SKXWriteResGroup94], (instregex "VPSLLDZ128rm(b?)(k?)(z?)")>;
def: InstRW<[SKXWriteResGroup94], (instregex "VPSLLDrm")>;
@@ -4266,9 +4266,9 @@ def: InstRW<[SKXWriteResGroup120], (inst
def: InstRW<[SKXWriteResGroup120], (instregex "VPRORVDZrm(b?)(k?)(z?)")>;
def: InstRW<[SKXWriteResGroup120], (instregex "VPRORVQZ256rm(b?)(k?)(z?)")>;
def: InstRW<[SKXWriteResGroup120], (instregex "VPRORVQZrm(b?)(k?)(z?)")>;
-def: InstRW<[SKXWriteResGroup120], (instregex "VPSIGNBYrm256")>;
-def: InstRW<[SKXWriteResGroup120], (instregex "VPSIGNDYrm256")>;
-def: InstRW<[SKXWriteResGroup120], (instregex "VPSIGNWYrm256")>;
+def: InstRW<[SKXWriteResGroup120], (instregex "VPSIGNBYrm")>;
+def: InstRW<[SKXWriteResGroup120], (instregex "VPSIGNDYrm")>;
+def: InstRW<[SKXWriteResGroup120], (instregex "VPSIGNWYrm")>;
def: InstRW<[SKXWriteResGroup120], (instregex "VPSLLDYrm")>;
def: InstRW<[SKXWriteResGroup120], (instregex "VPSLLDZ256m(b?)i(k?)(z?)")>;
def: InstRW<[SKXWriteResGroup120], (instregex "VPSLLDZ256rm(b?)(k?)(z?)")>;
@@ -4526,18 +4526,18 @@ def SKXWriteResGroup123 : SchedWriteRes<
let NumMicroOps = 4;
let ResourceCycles = [1,2,1];
}
-def: InstRW<[SKXWriteResGroup123], (instregex "MMX_PHADDSWrm64")>;
-def: InstRW<[SKXWriteResGroup123], (instregex "MMX_PHSUBSWrm64")>;
+def: InstRW<[SKXWriteResGroup123], (instregex "MMX_PHADDSWrm")>;
+def: InstRW<[SKXWriteResGroup123], (instregex "MMX_PHSUBSWrm")>;
def SKXWriteResGroup124 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort05]> {
let Latency = 8;
let NumMicroOps = 4;
let ResourceCycles = [2,1,1];
}
-def: InstRW<[SKXWriteResGroup124], (instregex "MMX_PHADDWrm64")>;
-def: InstRW<[SKXWriteResGroup124], (instregex "MMX_PHADDrm64")>;
-def: InstRW<[SKXWriteResGroup124], (instregex "MMX_PHSUBDrm64")>;
-def: InstRW<[SKXWriteResGroup124], (instregex "MMX_PHSUBWrm64")>;
+def: InstRW<[SKXWriteResGroup124], (instregex "MMX_PHADDWrm")>;
+def: InstRW<[SKXWriteResGroup124], (instregex "MMX_PHADDrm")>;
+def: InstRW<[SKXWriteResGroup124], (instregex "MMX_PHSUBDrm")>;
+def: InstRW<[SKXWriteResGroup124], (instregex "MMX_PHSUBWrm")>;
def SKXWriteResGroup125 : SchedWriteRes<[SKXPort4,SKXPort5,SKXPort237,SKXPort015]> {
let Latency = 8;
@@ -4643,9 +4643,9 @@ def SKXWriteResGroup135 : SchedWriteRes<
let ResourceCycles = [1,1];
}
def: InstRW<[SKXWriteResGroup135], (instregex "MMX_CVTPI2PSirm")>;
-def: InstRW<[SKXWriteResGroup135], (instregex "MMX_PMADDUBSWrm64")>;
+def: InstRW<[SKXWriteResGroup135], (instregex "MMX_PMADDUBSWrm")>;
def: InstRW<[SKXWriteResGroup135], (instregex "MMX_PMADDWDirm")>;
-def: InstRW<[SKXWriteResGroup135], (instregex "MMX_PMULHRSWrm64")>;
+def: InstRW<[SKXWriteResGroup135], (instregex "MMX_PMULHRSWrm")>;
def: InstRW<[SKXWriteResGroup135], (instregex "MMX_PMULHUWirm")>;
def: InstRW<[SKXWriteResGroup135], (instregex "MMX_PMULHWirm")>;
def: InstRW<[SKXWriteResGroup135], (instregex "MMX_PMULLWirm")>;
@@ -4811,10 +4811,10 @@ def SKXWriteResGroup143 : SchedWriteRes<
let NumMicroOps = 4;
let ResourceCycles = [2,1,1];
}
-def: InstRW<[SKXWriteResGroup143], (instregex "PHADDSWrm128")>;
-def: InstRW<[SKXWriteResGroup143], (instregex "PHSUBSWrm128")>;
-def: InstRW<[SKXWriteResGroup143], (instregex "VPHADDSWrm128")>;
-def: InstRW<[SKXWriteResGroup143], (instregex "VPHSUBSWrm128")>;
+def: InstRW<[SKXWriteResGroup143], (instregex "PHADDSWrm")>;
+def: InstRW<[SKXWriteResGroup143], (instregex "PHSUBSWrm")>;
+def: InstRW<[SKXWriteResGroup143], (instregex "VPHADDSWrm")>;
+def: InstRW<[SKXWriteResGroup143], (instregex "VPHSUBSWrm")>;
def SKXWriteResGroup144 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort015]> {
let Latency = 9;
@@ -5049,7 +5049,7 @@ def: InstRW<[SKXWriteResGroup149], (inst
def: InstRW<[SKXWriteResGroup149], (instregex "MIN(C?)PSrm")>;
def: InstRW<[SKXWriteResGroup149], (instregex "MULPDrm")>;
def: InstRW<[SKXWriteResGroup149], (instregex "MULPSrm")>;
-def: InstRW<[SKXWriteResGroup149], (instregex "PHMINPOSUWrm128")>;
+def: InstRW<[SKXWriteResGroup149], (instregex "PHMINPOSUWrm")>;
def: InstRW<[SKXWriteResGroup149], (instregex "PMADDUBSWrm")>;
def: InstRW<[SKXWriteResGroup149], (instregex "PMADDWDrm")>;
def: InstRW<[SKXWriteResGroup149], (instregex "PMULDQrm")>;
@@ -5133,7 +5133,7 @@ def: InstRW<[SKXWriteResGroup149], (inst
def: InstRW<[SKXWriteResGroup149], (instregex "VMULPSrm")>;
def: InstRW<[SKXWriteResGroup149], (instregex "VMULSDZrm(_Int)?(k?)(z?)")>;
def: InstRW<[SKXWriteResGroup149], (instregex "VMULSSZrm(_Int)?(k?)(z?)")>;
-def: InstRW<[SKXWriteResGroup149], (instregex "VPHMINPOSUWrm128")>;
+def: InstRW<[SKXWriteResGroup149], (instregex "VPHMINPOSUWrm")>;
def: InstRW<[SKXWriteResGroup149], (instregex "VPLZCNTDZ128rm(b?)(k?)(z?)")>;
def: InstRW<[SKXWriteResGroup149], (instregex "VPLZCNTQZ128rm(b?)(k?)(z?)")>;
def: InstRW<[SKXWriteResGroup149], (instregex "VPMADDUBSWZ128rm(b?)(k?)(z?)")>;
@@ -5214,8 +5214,8 @@ def SKXWriteResGroup154 : SchedWriteRes<
let NumMicroOps = 4;
let ResourceCycles = [2,1,1];
}
-def: InstRW<[SKXWriteResGroup154], (instregex "VPHADDSWrm256")>;
-def: InstRW<[SKXWriteResGroup154], (instregex "VPHSUBSWrm256")>;
+def: InstRW<[SKXWriteResGroup154], (instregex "VPHADDSWYrm")>;
+def: InstRW<[SKXWriteResGroup154], (instregex "VPHSUBSWYrm")>;
def SKXWriteResGroup155 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort015]> {
let Latency = 10;
Modified: llvm/trunk/lib/Target/X86/X86ScheduleZnver1.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ScheduleZnver1.td?rev=323402&r1=323401&r2=323402&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ScheduleZnver1.td (original)
+++ llvm/trunk/lib/Target/X86/X86ScheduleZnver1.td Wed Jan 24 20:45:30 2018
@@ -1067,12 +1067,12 @@ def : InstRW<[WriteMicrocoded], (instreg
// HADD, HSUB PS/PD
// PHADD|PHSUB (S) W/D.
-def : InstRW<[WriteMicrocoded], (instregex "MMX_PHADD(W?)r(r|m)64",
- "MMX_PHADDSWr(r|m)64",
- "MMX_PHSUB(W|D)r(r|m)64",
- "MMX_PHSUBSWrr64",
+def : InstRW<[WriteMicrocoded], (instregex "MMX_PHADD(W?)r(r|m)",
+ "MMX_PHADDSWr(r|m)",
+ "MMX_PHSUB(W|D)r(r|m)",
+ "MMX_PHSUBSWrr",
"(V?)PH(ADD|SUB)(W|D)(Y?)r(r|m)",
- "(V?)PH(ADD|SUB)SWr(r|m)(256)?")>;
+ "(V?)PH(ADD|SUB)SW(Y?)r(r|m)")>;
// PCMPGTQ.
Modified: llvm/trunk/test/MC/X86/x86_64-asm-match.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/X86/x86_64-asm-match.s?rev=323402&r1=323401&r2=323402&view=diff
==============================================================================
--- llvm/trunk/test/MC/X86/x86_64-asm-match.s (original)
+++ llvm/trunk/test/MC/X86/x86_64-asm-match.s Wed Jan 24 20:45:30 2018
@@ -2,7 +2,7 @@
// REQUIRES: asserts
// CHECK: AsmMatcher: found 4 encodings with mnemonic 'pshufb'
-// CHECK: Trying to match opcode MMX_PSHUFBrr64
+// CHECK: Trying to match opcode MMX_PSHUFBrr
// CHECK: Matching formal operand class MCK_VR64 against actual operand at index 1 (Memory: ModeSize=64,BaseReg=rip,Scale=1,Disp=CPI1_0): Opcode result: multiple operand mismatches, ignoring this opcode
// CHECK: Trying to match opcode PSHUFBrr
// CHECK: Matching formal operand class MCK_FR32 against actual operand at index 1 (Memory: ModeSize=64,BaseReg=rip,Scale=1,Disp=CPI1_0): Opcode result: multiple operand mismatches, ignoring this opcode
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