[PATCH] D42478: [AArch64] Improve v8.1-A code-gen for atomic load-and

[Oliver Stannard via Phabricator via llvm-commits]

olista01 created this revision.
olista01 added reviewers: mcrosier, gberry, christof.
Herald added subscribers: kristof.beyls, javed.absar, rengolin, aemerson.

Armv8.1-A added an atomic load-clear instruction (which performs bitwise
and with the complement of it's operand), but not a load-and
instruction. Our current code-generation for atomic load-and always
inserts an MVN instruction to invert its argument, even if it could be
folded into a constant or another instruction.

This adds lowering early in selection DAG to convert a load-and
operation into an xor with -1 and a load-clear, allowing the normal DAG
optimisations to work on it.

To do this, I've had to add a new ISD opcode, ATOMIC_LOAD_CLR. I don't
see any easy way to do this with an AArch64-specific ISD node, because
the code-generation for atomic operations assumes the SDNodes are of
type AtomicSDNode.

I've left the old tablegen patterns in because they are still needed for
global isel.


Repository:
  rL LLVM

https://reviews.llvm.org/D42478

Files:
  include/llvm/CodeGen/ISDOpcodes.h
  include/llvm/CodeGen/SelectionDAGNodes.h
  include/llvm/Target/TargetSelectionDAG.td
  lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
  lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
  lib/CodeGen/SelectionDAG/SelectionDAG.cpp
  lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
  lib/Target/AArch64/AArch64ISelLowering.cpp
  lib/Target/AArch64/AArch64ISelLowering.h
  lib/Target/AArch64/AArch64InstrAtomics.td
  test/CodeGen/AArch64/atomic-ops-lse.ll

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