[PATCH] D42477: [AArch64] Improve v8.1-A code-gen for atomic load-subtract

[Oliver Stannard via Phabricator via llvm-commits]

olista01 created this revision.
olista01 added reviewers: mcrosier, gberry, christof.
Herald added subscribers: kristof.beyls, javed.absar, rengolin, aemerson.

Armv8.1-A added an atomic load-add instruction, but not a load-subtract
instruction. Our current code-generation for atomic load-subtract always
inserts a NEG instruction to negate it's argument, even if it could be
folded into a constant or another instruction.

This adds lowering early in selection DAG to convert a load-subtract
operation into a subtract and a load-add, allowing the normal DAG
optimisations to work on it.

I've left the old tablegen patterns in because they are still needed for
global isel.

Some of the tests in this patch are copied from https://reviews.llvm.org/D35375 by Chad Rosier (which was abandoned).


Repository:
  rL LLVM

https://reviews.llvm.org/D42477

Files:
  lib/Target/AArch64/AArch64ISelLowering.cpp
  lib/Target/AArch64/AArch64ISelLowering.h
  test/CodeGen/AArch64/atomic-ops-lse.ll

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