[PATCH] D42088: [x86] shrink 'and' immediate values by setting the high bits (PR35907)

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a comment.

I removed the srl/and reversing transform from X86 to see if we did any better. But end up with an and with 65024 in from of the shift.

Part of the problem seems to be that we promote the srl using an any_extend and a zero_extend_inreg(an and) instead of using a zero_extend directly. Then simplifydemandedbits is able to mess with the and before we get a chance to run the DAG combine that combines and+any_extend into zero_extend. That combine requires the and to still be with 65535, but it had already been turned into 65024.


https://reviews.llvm.org/D42088